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1. 发明授权

US5019888A Circuit to improve electrostatic discharge protection 失效
标题翻译：电路改善静电放电保护
公开(公告)号：US5019888A
公开(公告)日：1991-05-28
申请号：US76622
申请日：1987-07-23
申请人： David B. Scott , Patrick W. Bosshart , James D. Gallia
发明人： David B. Scott , Patrick W. Bosshart , James D. Gallia
IPC分类号： H01L27/02
CPC分类号： H01L27/0251
摘要： An output buffer (26) comprises a plurality of transistors (28) arranged in parallel between an output pin (34) and ground (38). Resistors (30) are connected in series between the drain (30) of the transistors (28) and the output pin (34) to ensure that an electrostatic discharge generated through normal handling will be distributed substantially equally through each of the transistors (28), thus preventing damage to the output buffer (26).
摘要翻译：输出缓冲器（26）包括并排布置在输出引脚（34）和接地（38）之间的多个晶体管（28）。电阻器（30）串联连接在晶体管（28）的漏极（30）和输出引脚（34）之间，以确保通过正常处理产生的静电放电将基本上相等地分布通过每个晶体管（28），，从而防止对输出缓冲器（26）的损坏。

2. 发明申请

US20110041592A1 METHODS AND APPARATUSES FOR COMFORT/SUPPORT ANALYSIS OF A SLEEP SUPPORT MEMBER 有权
标题翻译：休闲支持会员舒适/支持分析的方法和设备
公开(公告)号：US20110041592A1
公开(公告)日：2011-02-24
申请号：US12920307
申请日：2008-11-14
申请人： Joe W. Schmoeller , David B. Scott , Robert D. Oexman , Joshua Carrier
发明人： Joe W. Schmoeller , David B. Scott , Robert D. Oexman , Joshua Carrier
IPC分类号： G01N3/40
CPC分类号： A47C31/123 , G01M99/001
摘要： A method of testing a sleep support member, the method including: identifying the sleep support member; determining a tested comfort/support value for the identified sleep support member before the identified sleep support member is provided to a customer; and determining whether the tested comfort/support value is within a predetermined tolerance level of a goal comfort/support value for the identified sleep support member. An apparatus for testing a sleep support member, the apparatus including: an identification unit configured to identify the sleep support member; a comfort/support testing unit configured to determine a tested comfort/support value for the identified sleep support member before the identified sleep support member is provided to a customer; and an analysis unit configured to determine whether the tested comfort/support value is within a predetermined tolerance level of a goal comfort/support value for the identified sleep support member.
摘要翻译：一种测试睡眠支撑构件的方法，所述方法包括：识别所述睡眠支撑构件; 在所识别的睡眠支持构件被提供给顾客之前，确定所识别的睡眠支持构件的测试舒适度/支持值; 以及确定测试的舒适度/支持值是否在所识别的睡眠支持构件的目标舒适度/支持值的预定公差水平内。一种用于测试睡眠支撑构件的装置，所述装置包括：识别单元，被配置为识别所述睡眠支撑构件; 舒适/支持测试单元，其被配置为在所识别的睡眠支持构件被提供给顾客之前确定所识别的睡眠支撑构件的测试舒适度/支持值; 以及分析单元，其被配置为确定所测试的舒适度/支持值是否在所识别的睡眠支持构件的目标舒适度/支持值的预定公差水平内。

3. 发明授权

US07376038B2 Fast access memory architecture 有权
标题翻译：快速访问内存架构
公开(公告)号：US07376038B2
公开(公告)日：2008-05-20
申请号：US11385151
申请日：2006-03-21
申请人： Sudha Thiruvengadam , Ramaprasath Vilangudipitchai , David B. Scott , Uming U. Ko , Alice Wang
发明人： Sudha Thiruvengadam , Ramaprasath Vilangudipitchai , David B. Scott , Uming U. Ko , Alice Wang
IPC分类号： G11C5/14
CPC分类号： G11C8/10
摘要： A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.
摘要翻译：一种包括控制逻辑和耦合到控制逻辑的存储器的计算机系统。存储器包括用于在控制逻辑和位单元之间传送数据的多个比特单元和位线。控制逻辑向存储器提供目标位单元的地址。在单个时钟周期内，存储器使用地址来激活目标比特单元，以预先耦合到目标比特单元的位线，并访问目标比特单元。

4. 发明授权

US07307471B2 Adaptive voltage control and body bias for performance and energy optimization 有权
标题翻译：用于性能和能量优化的自适应电压控制和体偏置
公开(公告)号：US07307471B2
公开(公告)日：2007-12-11
申请号：US11213477
申请日：2005-08-26
申请人： Gordon Gammie , Alice Wang , Uming U. Ko , David B. Scott
发明人： Gordon Gammie , Alice Wang , Uming U. Ko , David B. Scott
IPC分类号： G05F1/565
CPC分类号： H03K19/0008 , H03K19/00384
摘要： A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device also comprises a second tracking element coupled to the processing module. The second tracking element produces a second value indicative of a second estimated speed associated with the circuitry. The processing module compares each of the first and second values to respective target values and causes a voltage output to be adjusted based on the comparisons. The first and second tracking elements comprise a plurality of transistors, at least some of the transistors selectively provided with a transistor bias voltage to adjust transistor speed.
摘要翻译：一种用于自适应地控制提供给设备附近的电路的电压的装置，包括耦合到处理模块的处理模块和第一跟踪元件。第一跟踪元件产生指示与电路相关联的第一估计速度的第一值。该装置还包括耦合到处理模块的第二跟踪元件。第二跟踪元件产生指示与电路相关联的第二估计速度的第二值。处理模块将第一和第二值中的每一个与各自的目标值进行比较，并且基于比较使得电压输出被调整。第一和第二跟踪元件包括多个晶体管，至少一些晶体管选择性地提供晶体管偏置电压以调整晶体管速度。

5. 发明授权

US06831337B2 Transistor circuit with varying resistance lightly doped diffused regions for electrostatic discharge (“ESD”) protection 有权
标题翻译：具有不同电阻的晶体管电路轻掺杂扩散区用于静电放电（“ESD”）保护
公开(公告)号：US06831337B2
公开(公告)日：2004-12-14
申请号：US10622052
申请日：2003-07-17
申请人： Zhiqiang Wu , David B. Scott
发明人： Zhiqiang Wu , David B. Scott
IPC分类号： H01L2972
CPC分类号： H01L29/66659 , H01L27/0266 , H01L29/0692 , H01L29/7835
摘要： A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.
摘要翻译：一种在半导体有源区（78）中形成晶体管（70）的方法。该方法形成与半导体有源区域固定关系的栅极结构（G2），从而限定与第一栅极结构侧壁相邻的第一源极/漏极区域（R1）和邻近第二侧壁栅极的第二源极/漏极区域（R2）结构体。该方法还形成在第一源极/漏极区域中形成并在栅极结构下方延伸的轻掺杂扩散区域（801），其中轻掺杂扩散区域包括与栅极结构平行的方向上的变化的电阻。

6. 发明授权

US06249452B1 Semiconductor device having offset twisted bit lines 有权
标题翻译：具有偏移扭转位线的半导体器件
公开(公告)号：US06249452B1
公开(公告)日：2001-06-19
申请号：US09400694
申请日：1999-09-22
申请人： David B. Scott
发明人： David B. Scott
IPC分类号： G11C508
CPC分类号： G11C7/18 , G03F7/2022 , H01L23/528 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A compact data line arrangement (600) includes “twisted” data line pairs (604a-604c) disposed in a first direction. Each twisted data line pair (604a-604c) includes an upper segment pair (608a-608f) that is connected to a lower segment pair (610a-610f) by a twist structure (612a-612c). The upper and lower segment pairs (608a-608f and 610a-610f) can be formed with a first pitch using phase-shifted lithography. The twist structures (612a-612c) are formed from a second conductive layer, and have a greater pitch than the first pitch. The twist structures (612a-612c) are generally arranged in a second direction that is perpendicular to the first direction. Selected twist structures (612b) are offset in the first direction with respect to adjacent twist structures (612a and 612c). The offset twist structures (612a-612c) allow supplemental conductive lines (618) to be formed from the first conductive layer that extend in the first direction, between adjacent offset twist structures (612a and 612b).
摘要翻译：紧凑型数据线装置（600）包括沿第一方向设置的“扭曲”数据线对（604a-604c）。每个扭绞数据线对（604a-604c）包括通过扭曲结构（612a-612c）连接到下部段对（610a-610f）的上段对（608a-608f）。上段和下段对（608a-608f和610a-610f）可以使用相移光刻形成具有第一间距。扭转结构（612a-612c）由第二导电层形成，并且具有比第一间距更大的间距。扭转结构（612a-612c）通常沿垂直于第一方向的第二方向布置。选定的扭转结构（612b）相对于相邻的扭转结构（612a和612c）沿第一方向偏移。偏移扭转结构（612a-612c）允许在相邻的偏移扭曲结构（612a和612b）之间从在第一方向上延伸的第一导电层形成补充导线（618）。

7. 发明授权

US06178136B1 Semiconductor memory device having Y-select gate voltage that varies according to memory cell access operation 有权
标题翻译：具有根据存储单元访问操作而变化的Y选择栅极电压的半导体存储器件
公开(公告)号：US06178136B1
公开(公告)日：2001-01-23
申请号：US09405264
申请日：1999-09-23
申请人： Heng-Chih Lin , Takumi Nasu , David B. Scott
发明人： Heng-Chih Lin , Takumi Nasu , David B. Scott
IPC分类号： G11C700
CPC分类号： G11C11/4096 , G11C7/1048
摘要： A dynamic random access memory (DRAM) includes a Y-select circuit (218) that connects a pair of bit lines (204a and 204b) to a pair of sense nodes (210a and 210b). The Y-select circuit (218) provides a first impedance in a read operation, and a second impedance that is lower than the first impedance, in a write operation. Changes in Y-select circuit (218) impedance are achieved by driving transistors (N210a and N210b) within the Y-select circuit (218) with a first voltage during a read operation, and a second voltage during a write operation.
摘要翻译：动态随机存取存储器（DRAM）包括将一对位线（204a和204b）连接到一对感测节点（210a和210b）的Y选择电路（218）。在写入操作中，Y选择电路（218）在读取操作中提供第一阻抗，并且提供低于第一阻抗的第二阻抗。通过在读取操作期间以第一电压驱动Y选择电路（218）内的晶体管（N210a和N210b）以及在写入操作期间的第二电压来实现Y选择电路（218）阻抗的变化。

8. 发明授权

US5848450A Air bed control 失效
标题翻译：气床控制
公开(公告)号：US5848450A
公开(公告)日：1998-12-15
申请号：US611381
申请日：1996-03-05
申请人： Robert D. Oexman , David B. Scott
发明人： Robert D. Oexman , David B. Scott
IPC分类号： A47C27/10 , A47C27/08
CPC分类号： A47C27/083 , A47C27/082 , A47C27/10 , A61G7/05769 , A61G2203/34
摘要： An airbed having multi-zone air mattress is provided having a control that can identify the configuration of any of a plurality of hand control units connected thereto and can interpret control functions differently based on the identified unit configuration. A plurality of normally closed valves seal pressures in each of the zones when power to an air pump is off while mattress zone pressures are constantly monitored and the measurements sent by the control through a communications port for monitoring of the motion or care of a user of the bed and for analysis and diagnosis. When pump power is on, the pressure in the zones is regulated at predetermined pressure settings ideal for the user. Deviations from ideal pressure cause a programmed controller to calculate inflation or deflation times for the respective zones that would be required to inflate or exhaust the zones to the desired pressures. Ideal pressures for individual users are automatically calculated by inflating the zones to initial pressures and sealing them. Then, a user reclines on the bed and pressures are measured. From the measured pressures, ideal pressure settings are calculated that will support the user in an ideal manner, such as maintaining the user in an ideal sleeping posture with a minimum amount of pressure in the zones. The sitting up of the user, the sitting of the user on the edge of the bed, the adjustment of bed inclination angles and other non-reclining conditions are detected by analysis of the pressures in the zones or information from other sources to set pressures particularly suited to such conditions.
摘要翻译：提供了具有多区域空气床垫的空气床，其具有可以识别与其连接的多个手动控制单元中的任何一个的配置的控制，并且可以基于所识别的单元配置来不同地解释控制功能。多个常闭阀门密封每个区域中的压力，当空气泵的动力关闭时，床垫区域压力被不断监测，并且由控制器通过通信端口发送的测量结果用于监视用户的运动或保养床和分析诊断。当泵浦电源打开时，区域中的压力被调节到预定的压力设置，适合用户使用。与理想压力的偏差导致编程控制器计算将各区域充气或排出到所需压力所需的各个区域的膨胀或放气时间。通过将区域充气到初始压力并将其密封，可以自动计算个人用户的理想压力。然后，用户在床上倾斜并测量压力。根据测量的压力，计算理想的压力设置，其将以理想的方式支持用户，例如在区域中以最小的压力维持使用者处于理想的睡眠姿势。通过分析区域内的压力或来自其他来源的信息来特别设定压力来检测使用者的坐姿，使用者在床边缘的坐姿，床倾角的调整和其他不倾斜的条件适合这种条件。

9. 发明授权

US5656524A Method of forming a polysilicon resistor using an oxide, nitride stack 失效
标题翻译：使用氧化物，氮化物叠层形成多晶硅电阻器的方法
公开(公告)号：US5656524A
公开(公告)日：1997-08-12
申请号：US478301
申请日：1995-06-07
申请人： Robert H. Eklund , Douglas A. Prinslow , David B. Scott
发明人： Robert H. Eklund , Douglas A. Prinslow , David B. Scott
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/70
CPC分类号： H01L28/20
摘要： A polysilicon resistor (40) includes a field oxide layer (12) and a polysilicon layer (20) that covers a portion of field oxide layer (12). The polysilicon layer (20) possesses a predetermined electrical resistance value. Nitride/oxide stack (42) covers a predetermined portion of the polysilicon layer (20) and forms at least one exposed location of polysilicon layer (20) on which not to implant a dopant to achieve a predetermined resistance value. Silicide layer (34) covers exposed location.
摘要翻译：多晶硅电阻器（40）包括场氧化物层（12）和覆盖一部分场氧化物层（12）的多晶硅层（20）。多晶硅层（20）具有预定的电阻值。氮化物/氧化物堆叠（42）覆盖多晶硅层（20）的预定部分并且形成多晶硅层（20）的至少一个暴露位置，在其上不注入掺杂剂以实现预定电阻值。硅化物层（34）覆盖暴露位置。

10. 发明授权

US5021851A NMOS source/drain doping with both P and As 失效
标题翻译：具有P和As的NMOS源极/漏极掺杂
公开(公告)号：US5021851A
公开(公告)日：1991-06-04
申请号：US453097
申请日：1989-12-13
申请人： Roger A. Haken , David B. Scott
发明人： Roger A. Haken , David B. Scott
IPC分类号： H01L21/22 , H01L21/225 , H01L29/08 , H01L29/167 , H01L29/78
CPC分类号： H01L21/2253 , H01L21/22 , H01L29/0847 , H01L29/167 , H01L29/78 , H01L29/7836 , Y10S257/917
摘要： A process for forming N-channel MOS sources and drains, by implanting both phosphorus and arsenic. The high diffusivity of phosphorus causes it to diffuse in advance of the bulk of the arsenic, so that, after annealing, the source/drain regions have graded regions of gradually decreasing conductivity adjacent to the end of the channels. Thus the electric potential gradient at the ends of the channels is reduced, and impact ionization and hot carrier effects are avoided. The effective radius of the source (or drain) junction is increased, providing increased breakdown voltage.
摘要翻译：通过植入磷和砷来形成N沟道MOS源和漏极的工艺。磷的高扩散性使其在大部分砷之前扩散，使得在退火之后，源/漏区具有与通道末端相邻的逐渐降低的导电性的渐变区域。因此，通道末端的电位梯度减小，并且避免了冲击电离和热载流子效应。源（或漏极）结的有效半径增加，提供增加的击穿电压。

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