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1. 发明申请

US20080114965A1 BUCKETS OF COMMANDS IN A MULTIPROCESSOR-BASED VERIFICATION ENVIRONMENT 失效
标题翻译：基于多处理器验证环境的命令框
公开(公告)号：US20080114965A1
公开(公告)日：2008-05-15
申请号：US11972690
申请日：2008-01-11
申请人： David Atoji , Ruchi Chandra , Robert Likovich
发明人： David Atoji , Ruchi Chandra , Robert Likovich
IPC分类号： G06F9/312
CPC分类号： G06F11/263
摘要： The present invention provides a method and system for providing a legal sequential combination of commands for verification testing of a computer system. Executable test commands are used to form sequentially ordered “buckets” of commands, wherein each bucket command sequence is legal under at least one rule. The buckets may be arranged in any sequential order, wherein a composite command sequence of the combined commands remains legal under the at least one rule. A further advantage of the invention is that wait/noop commands may be inserted within and between the buckets, extending the testing capabilities of the present invention into corner cases.
摘要翻译：本发明提供了一种用于提供用于计算机系统的验证测试的命令的合法顺序组合的方法和系统。可执行测试命令用于形成顺序排列的命令“桶”，其中每个桶命令序列在至少一个规则下是合法的。桶可以以任何顺序排列，其中组合命令的复合命令序列在至少一个规则下保持合法。本发明的另一个优点是可以将等待/ noop命令插入到桶内和桶之间，从而将本发明的测试能力扩展到角箱。

2. 发明申请

US20050015686A1 Buckets of commands in a multiprocessor-based verification environment 失效
标题翻译：基于多处理器的验证环境中的各种命令
公开(公告)号：US20050015686A1
公开(公告)日：2005-01-20
申请号：US10620472
申请日：2003-07-16
申请人： David Atoji , Ruchi Chandra , Robert Likovich
发明人： David Atoji , Ruchi Chandra , Robert Likovich
IPC分类号： G06F11/00 , G06F11/263
CPC分类号： G06F11/263
摘要： The present invention provides a method and system for providing a legal sequential combination of commands for verification testing of a computer system. Executable test commands are used to form sequentially ordered “buckets” of commands, wherein each bucket command sequence is legal under at least one rule. The buckets may be arranged in any sequential order, wherein a composite command sequence of the combined commands remains legal under the at least one rule. A further advantage of the invention is that wait/noop commands may be inserted within and between the buckets, extending the testing capabilities of the present invention into corner cases.
摘要翻译：本发明提供了一种用于提供用于计算机系统的验证测试的命令的合法顺序组合的方法和系统。可执行测试命令用于形成顺序排列的命令“桶”，其中每个桶命令序列在至少一个规则下是合法的。桶可以以任何顺序排列，其中组合命令的复合命令序列在至少一个规则下保持合法。本发明的另一个优点是可以将等待/ noop命令插入到桶内和桶之间，从而将本发明的测试能力扩展到角箱。

3. 发明申请

US20050271058A1 Cell or frame assembly method and apparatus optimizing the moving of data 失效
标题翻译：单元或框架组装方法和设备优化数据移动
公开(公告)号：US20050271058A1
公开(公告)日：2005-12-08
申请号：US11198828
申请日：2005-08-05
申请人： David Atoji
发明人： David Atoji
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L49/90 , H04L49/9094 , H04L2012/5652 , H04L2012/5679
摘要： In a network node, a method and apparatus for assembling fixed cell length cells resulting from the segmenting of variable length frames into cells. The hardware implementations of the preferred embodiments of the invention comprise a finite state machine which handles three processes at the same time, one for fetching the frame data stored in a storage unit, the data store, one for moving data from the frame data and control block data to the cell and one for outputting cell data. The other components are a counter for the pointing to the frame and a multiplexer for selecting the correct data to form the cell. The simple finite state machine is able to repetitively build all the cells corresponding to a frame because a cell pattern always applies to these cells with only two constraints. The first is to have the cell size be 64 unit (4 column unit by 16 row unit where a unit can be a byte, bit or any multiplier of bits or bytes) with a 6 unit cell header and 10 unit frame header; the second is to have the insert and overlay field have to be even. This method and apparatus can be used whenever the frame are modified during the segmenting processing by replacing a field by a definite value or when a new field is inserted in the frame or even if frames are packed into one cell.
摘要翻译：在一个网络节点中，一种用于将由可变长度帧分割得到的固定单元长度单元组装成单元的方法和装置。本发明的优选实施例的硬件实现包括一个同时处理三个进程的有限状态机，一个用于取出存储在存储单元中的帧数据，数据存储器，一个用于从帧数据移动数据和控制将数据块传输到单元，一个用于输出单元数据。其他组件是用于指向帧的计数器和用于选择正确数据以形成单元的多路复用器。简单的有限状态机能够重复地构建对应于一个帧的所有单元，因为单元格图案总是仅以两个约束应用于这些单元。第一个是使单元大小为64单位（4列单位乘16行单位，单位可以是一个字节，位或任何位或字节的乘法器），具有6个单元格标题和10个单位帧标题; 第二个是使插入和覆盖字段必须均匀。只要在分段处理期间通过将字段替换定义值或者当新字段插入到帧中时或者即使帧被包装到一个单元中时，也可以使用该方法和装置。

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