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1. 发明授权

US07895028B2 Structure for increasing fuse programming yield 有权
标题翻译：提高保险丝编程产量的结构
公开(公告)号：US07895028B2
公开(公告)日：2011-02-22
申请号：US11775531
申请日：2007-07-10
申请人： Darren Lane Anand , Michael Richard Ouellette , Michael Anthony Ziegerhofer
发明人： Darren Lane Anand , Michael Richard Ouellette , Michael Anthony Ziegerhofer
IPC分类号： G06F17/50
CPC分类号： G11C29/44 , G11C17/165 , G11C29/027 , G11C29/802
摘要： A design structure which enables e-fuse memory repair. The design structure uses a compressed bit string to generate another bit string based on a select value. The select value provides instructions to an encoding logic element, which generates a second bit string. For example, the select value may instruct the encoding logic to create a duplicate copy of each bit in the compressed bit string to generate a 2n-bit string. Once the fuses are programmed using the second bit string, the fuse values are read out as a third string, which is decoded by a decoding logic element according to the select value, thereby improving memory repair.
摘要翻译：一种能够进行电子保险丝内存修复的设计结构。设计结构使用压缩比特串根据选择值生成另一个比特串。该选择值向编码逻辑元件提供指令，该编码逻辑元件产生第二位串。例如，选择值可以指示编码逻辑在压缩比特串中创建每个比特的重复副本以生成2n比特串。一旦使用第二位串编程熔丝，则将熔丝值作为第三串读出，其由解码逻辑元件根据选择值解码，从而改善存储器修复。

2. 发明授权

US07251756B2 Method and apparatus for increasing fuse programming yield through preferred use of duplicate data 有权
标题翻译：通过优选使用重复数据来增加保险丝编程产量的方法和装置
公开(公告)号：US07251756B2
公开(公告)日：2007-07-31
申请号：US10908033
申请日：2005-04-26
申请人： Darren Lane Anand , Michael Richard Ouellette , Michael Anthony Ziegerhofer
发明人： Darren Lane Anand , Michael Richard Ouellette , Michael Anthony Ziegerhofer
IPC分类号： G11C29/00
CPC分类号： G11C17/165 , G11C29/027 , G11C29/4401 , G11C29/72
摘要： Integrated circuit memory is tested to discover defective memory elements. To replace the defective memory elements, spare memory elements are selected and a string is generated to indicate which ones of the spares replace which ones of the defective memory elements. The number of bits of the string depend upon how many of the memory elements are defective. Although a certain number of the memory elements are defective, which determines the number of the string bits, nevertheless, a number of fuses to program on the integrated circuit is determined responsive to how many fuses are available for programming relative to the number of the binary string bits. That is, if more fuses are available than a certain threshold number relative to the number of string bits (as is preferred), then more than the threshold number are programmed. If not, then only that certain threshold number of fuses are programmed.
摘要翻译：测试集成电路存储器以发现有缺陷的存储器元件。为了更换有缺陷的存储器元件，选择备用存储器元件，并且生成字符串以指示哪些备用件替换有缺陷存储器元件中的哪一个。字符串的位数取决于多少存储器元件有缺陷。尽管一定数量的存储器元件是有缺陷的，这确定了串比特的数目，然而，确定集成电路上编程的多个保险丝的响应是相对于二进制数的编号有多少个熔丝可用于编程字符串位。也就是说，如果比相对于字符串位数（优选的）更多的保险丝可用于某个阈值数，则多于阈值编号。如果没有，那么只有该阈值数量的保险丝被编程。

3. 发明授权

US07688654B2 Structure for differential eFUSE sensing without reference fuses 有权
标题翻译：不带参考保险丝的差分eFUSE检测结构
公开(公告)号：US07688654B2
公开(公告)日：2010-03-30
申请号：US11769925
申请日：2007-06-28
申请人： Darren Lane Anand , John Atkinson Fifield , Michael Richard Ouellette
发明人： Darren Lane Anand , John Atkinson Fifield , Michael Richard Ouellette
IPC分类号： G11C11/063
CPC分类号： G11C17/16 , G11C17/18
摘要： A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.
摘要翻译：一种设计结构，包括差分熔丝感测系统，其包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到保险丝腿的第一输入节点的差分读出放大器和耦合到参考电压的第二节点。保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。

4. 发明申请

US20080001251A1 STRUCTURE FOR DIFFERENTIAL EFUSE SENSING WITHOUT REFERENCE FUSES 有权
标题翻译：不参考熔丝的不同EFEX感应结构
公开(公告)号：US20080001251A1
公开(公告)日：2008-01-03
申请号：US11769925
申请日：2007-06-28
申请人： Darren Lane Anand , John Atkinson Fifield , Michael Richard Ouellette
发明人： Darren Lane Anand , John Atkinson Fifield , Michael Richard Ouellette
IPC分类号： H01L29/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.
摘要翻译：一种设计结构，包括差分熔丝感测系统，其包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到保险丝腿的第一输入节点的差分读出放大器和耦合到参考电压的第二节点。保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。

5. 发明授权

US08570820B2 Selectable repair pass masking 有权
标题翻译：可选择修复通过掩蔽
公开(公告)号：US08570820B2
公开(公告)日：2013-10-29
申请号：US13042881
申请日：2011-03-08
申请人： Kevin William Gorman , John Robert Goss , Michael Richard Ouellette , Troy Joseph Perry , Michael Anthony Ziegerhofer
发明人： Kevin William Gorman , John Robert Goss , Michael Richard Ouellette , Troy Joseph Perry , Michael Anthony Ziegerhofer
IPC分类号： G11C7/10
CPC分类号： G11C29/4401 , G11C29/76 , G11C29/802 , G11C2029/0401 , G11C2229/726
摘要： The present invention relates to a method and circuit for selectively repairing an embedded memory module having memory elements in an integrated circuit chip. The method includes performing a plurality of tests on the embedded memory module under operating conditions to identify a plurality of non-operational memory elements in the embedded memory module and, in response to identifying the non-operational memory elements, generating a plurality of corresponding repair solutions. The method further includes storing the plurality of corresponding repair solutions in a non-volatile storage element and determining from a mask a subset of the plurality of repair solutions that should be restored.
摘要翻译：本发明涉及一种用于选择性地修复在集成电路芯片中具有存储元件的嵌入式存储器模块的方法和电路。该方法包括在操作条件下对嵌入式存储器模块执行多个测试以识别嵌入式存储器模块中的多个非操作存储器元件，并且响应于识别非操作存储器元件，生成多个相应的修复解决方案该方法还包括将多个相应的修复解决方案存储在非易失性存储元件中，并且从掩模确定应该被恢复的多个修复解决方案的子集。

6. 发明申请

US20120230136A1 SELECTABLE REPAIR PASS MASKING 有权
标题翻译：可选修理通道掩蔽
公开(公告)号：US20120230136A1
公开(公告)日：2012-09-13
申请号：US13042881
申请日：2011-03-08
申请人： Kevin William Gorman , John Robert Goss , Michael Richard Ouellette , Troy Joseph Perry , Michael Anthony Ziegerhofer
发明人： Kevin William Gorman , John Robert Goss , Michael Richard Ouellette , Troy Joseph Perry , Michael Anthony Ziegerhofer
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/76 , G11C29/802 , G11C2029/0401 , G11C2229/726
摘要： The present invention relates to a method and circuit for selectively repairing an embedded memory module having memory elements in an integrated circuit chip. The method comprises performing a plurality of tests on the embedded memory module under operating conditions to identify a plurality of non-operational memory elements in the embedded memory module and, in response to identifying the non-operational memory elements, generating a plurality of corresponding repair solutions. The method further comprises storing the plurality of corresponding repair solutions in a non-volatile storage element and determining from a mask a subset of the plurality of repair solutions that should be restored.
摘要翻译：本发明涉及一种用于选择性地修复在集成电路芯片中具有存储元件的嵌入式存储器模块的方法和电路。该方法包括在操作条件下对嵌入式存储器模块执行多个测试以识别嵌入式存储器模块中的多个非操作存储器元件，并且响应于识别非操作存储器元件，生成多个相应的修复解决方案该方法还包括将多个对应的修复解决方案存储在非易失性存储元件中，并从掩模确定应该被恢复的多个修复解决方案的子集。

7. 发明授权

US07739637B2 Partial good schema for integrated circuits having parallel execution units 失效
标题翻译：具有并行执行单元的集成电路的部分良好架构
公开(公告)号：US07739637B2
公开(公告)日：2010-06-15
申请号：US12362541
申请日：2009-01-30
申请人： Kenneth Joseph Goodnow , Michael Richard Ouellette , Stephen Gerard Shuma , Peter Albert Twombly
发明人： Kenneth Joseph Goodnow , Michael Richard Ouellette , Stephen Gerard Shuma , Peter Albert Twombly
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Processing engines (PE's) disposed on the substrate. Each processing engine includes a measurement and storage unit, and a PE controller coupled to each of the processing engines. The processing engines perform self-tests and store the results of the self-tests in the measurement and storage unit. The PE controller reads the results and selects a sub-set of processing engines based on the results and an optimization algorithm.
摘要翻译：处理引擎（PE）设置在基板上。每个处理引擎包括测量和存储单元以及耦合到每个处理引擎的PE控制器。处理引擎执行自检并将测试结果存储在测量和存储单元中。 PE控制器根据结果和优化算法读取结果并选择一组处理引擎。

8. 发明申请

US20090256591A1 STRUCTURE FOR SYSTEMS AND METHODS OF MANAGING A SET OF PROGRAMMABLE FUSES ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：用于系统的结构和在集成电路上管理一组可编程熔丝的方法
公开(公告)号：US20090256591A1
公开(公告)日：2009-10-15
申请号：US12103519
申请日：2008-04-15
申请人： John Atkinson Fifield , Michael Richard Ouellette
发明人： John Atkinson Fifield , Michael Richard Ouellette
IPC分类号： H03K19/173
CPC分类号： H03K19/1733
摘要： Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.
摘要翻译：公开了一种用于在集成电路上管理一组可编程熔丝的系统和方法的设计结构。

9. 发明授权

US06229754B1 Write through function for a memory 有权
标题翻译：写入内存的功能
公开(公告)号：US06229754B1
公开(公告)日：2001-05-08
申请号：US09501393
申请日：2000-02-09
申请人： Eric Lee Carter , Moon Ho Lee , Michael Richard Ouellette , Geoffrey Wang , Michael Hemsley Wood
发明人： Eric Lee Carter , Moon Ho Lee , Michael Richard Ouellette , Geoffrey Wang , Michael Hemsley Wood
IPC分类号： G11C800
CPC分类号： G11C8/16
摘要： A multi-port electronic memory has a write through capability. Control features for enabling a write through path to an output and subsequently disabling without causing data errors due to design and technology variations are provided. Control features are especially beneficial for use with compilable SRAM books.
摘要翻译：多端口电子存储器具有写入功能。提供了用于启用到输出的写入路径并随后禁用而不会由于设计和技术变化而导致数据错误的控制特征。控制功能特别适用于可编译SRAM书籍。

10. 发明授权

US07139944B2 Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability 有权
标题翻译：用于确定集成电路设备实现最佳可靠性所需的最小后期制作测试时间的方法和系统
公开(公告)号：US07139944B2
公开(公告)日：2006-11-21
申请号：US10604887
申请日：2003-08-25
申请人： Tange Nan Barbour , Thomas S. Barnett , Matthew Sean Grady , William Vincent Huott , Michael Richard Ouellette
发明人： Tange Nan Barbour , Thomas S. Barnett , Matthew Sean Grady , William Vincent Huott , Michael Richard Ouellette
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G11C29/44 , G11C29/56008 , G11C2029/1208 , G11C2029/4402
摘要： A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integrated circuit device are counted and this count serves as a basis for determining the minimum test time. A higher number of DEFECTS results in longer post production testing in order to achieve optimum reliability of the integrated circuit device. The number of DEFECTS can be counted on a device internal to the integrated circuit device and made available to determine the minimum required test time. The number of DEFECTS can also be obtained external to the integrated circuit device by intercepting information routed to another device. Information provided internally and externally can also reveal the physical location of DEFECTS to further refine the minimum required test time.
摘要翻译：一种用于在集成电路器件上确定最小后期制作测试时间以实现利用缺陷计数的该器件的最佳可靠性的方法和系统。对集成电路装置上的缺陷单元或缺陷单元（DEFECTS）的有缺陷单元的数量进行计数，该计数作为确定最小测试时间的基础。更高数量的缺陷导致更长的后期测试，以实现集成电路器件的最佳可靠性。 DEFECTS的数量可以在集成电路设备内部的设备上进行计数，并可用于确定最低要求的测试时间。还可以通过拦截路由到另一设备的信息，在集成电路设备外部获得缺陷数量。内部和外部提供的信息还可以显示缺陷的物理位置，以进一步完善最低要求的测试时间。

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