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1. 发明授权

US07917806B2 System and method for indicating status of an on-chip power supply system 有权
标题翻译：用于指示片上电源系统状态的系统和方法
公开(公告)号：US07917806B2
公开(公告)日：2011-03-29
申请号：US11958680
申请日：2007-12-18
申请人： Darren L. Anand , John A. Fifield , Kevin W. Gorman
发明人： Darren L. Anand , John A. Fifield , Kevin W. Gorman
IPC分类号： G06F11/00
CPC分类号： G01R19/16552 , G11C11/401 , G11C29/02 , G11C29/021 , G11C29/44 , G11C2029/0401 , G11C2029/4402
摘要： The status of multiple on-chip power supply systems is indicated for use in modifying chip test flow and diagnosing chip failure. Digital compliance signals are received, each compliance signal associated with one of multiple on-chip power supplies. Each power supply has an associated compliance level, and each compliance signal indicates whether its associated power supply is operating at the associated compliance level. The compliance signals are converted into a power supply status signal indicating status of the compliance signals associated with the power supply. The power supply status signal is output. If a power supply is operating at its associated compliance level, the output power supply status signal indicates that the power supply is passing. If the power supply is not operating at its associated compliance level, the output power supply status signal indicates that the power supply is failing. If a power supply is failing, a memory test may be aborted, simplifying chip failure diagnosis.
摘要翻译：多片式电源系统的状态被指示用于修改芯片测试流程和诊断芯片故障。接收数字符合性信号，每个合规信号与多个片上电源之一相关联。每个电源具有相关的合规级别，并且每个合规信号指示其相关联的电源是否以相关联的合规级别运行。合规信号被转换成指示与电源相关联的符合性信号的状态的电源状态信号。输出电源状态信号。如果电源工作在相关的合规级别，则输出电源状态信号表示电源正在通过。如果电源不在其相关的合规级别运行，则输出电源状态信号表示电源出现故障。如果电源出现故障，可能会中断内存测试，从而简化了芯片故障诊断。

2. 发明申请

US20090158092A1 SYSTEM AND METHOD FOR INDICATING STATUS OF AN ON-CHIP POWER SUPPLY SYSTEM 有权
标题翻译：用于表示片上电源系统的状态的系统和方法
公开(公告)号：US20090158092A1
公开(公告)日：2009-06-18
申请号：US11958680
申请日：2007-12-18
申请人： Darren L. Anand , John A. Fifield , Kevin W. Gorman
发明人： Darren L. Anand , John A. Fifield , Kevin W. Gorman
IPC分类号： G06F11/07 , G06F11/30
CPC分类号： G01R19/16552 , G11C11/401 , G11C29/02 , G11C29/021 , G11C29/44 , G11C2029/0401 , G11C2029/4402
摘要： The status of multiple on-chip power supply systems is indicated for use in modifying chip test flow and diagnosing chip failure. Digital compliance signals are received, each compliance signal associated with one of multiple on-chip power supplies. Each power supply has an associated compliance level, and each compliance signal indicates whether its associated power supply is operating at the associated compliance level. The compliance signals are converted into a power supply status signal indicating status of the compliance signals associated with the power supply. The power supply status signal is output. If a power supply is operating at its associated compliance level, the output power supply status signal indicates that the power supply is passing. If the power supply is not operating at its associated compliance level, the output power supply status signal indicates that the power supply is failing. If a power supply is failing, a memory test may be aborted, simplifying chip failure diagnosis.
摘要翻译：多片式电源系统的状态被指示用于修改芯片测试流程和诊断芯片故障。接收数字符合性信号，每个合规信号与多个片上电源之一相关联。每个电源具有相关的合规级别，并且每个合规信号指示其相关联的电源是否以相关联的合规级别运行。合规信号被转换成指示与电源相关联的符合性信号的状态的电源状态信号。输出电源状态信号。如果电源工作在相关的合规级别，则输出电源状态信号表示电源正在通过。如果电源不在其相关的合规级别运行，则输出电源状态信号表示电源出现故障。如果电源出现故障，可能会中断内存测试，从而简化了芯片故障诊断。

3. 发明授权

US08484543B2 Fusebay controller structure, system, and method 有权
标题翻译： Fusebay控制器结构，系统和方法
公开(公告)号：US08484543B2
公开(公告)日：2013-07-09
申请号：US13204929
申请日：2011-08-08
申请人： Darren L. Anand , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Darren L. Anand , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： H03M13/00
CPC分类号： G06F11/1048 , G11C17/165 , G11C29/027 , G11C2029/0411
摘要： Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.
摘要翻译：选择性地将错误校正应用于数据，例如要存储在ASIC或其他半导体器件上的BIST / BISR的保险丝盒中的修复数据。可以包括重复的位校正和纠错码状态机，并且可以使用诸如多路复用器的选择器来实现一种或两种类型的校正。每个状态机可以包括诸如“粘性位”的指示符，当其遇到类型的校正时可以被激活。指示器可用于在包括本发明的实施例的部件的制造测试期间开发质量和产量控制标准。

4. 发明申请

US20130042166A1 FUSEBAY CONTROLLER STRUCTURE, SYSTEM, AND METHOD 有权
标题翻译： FUSEBAY控制器结构，系统和方法
公开(公告)号：US20130042166A1
公开(公告)日：2013-02-14
申请号：US13204929
申请日：2011-08-08
申请人： Darren L. Anand , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
发明人： Darren L. Anand , Kevin W. Gorman , Michael R. Ouellette , Michael A. Ziegerhofer
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： G06F11/1048 , G11C17/165 , G11C29/027 , G11C2029/0411
摘要： Error correction is selectively applied to data, such as repair data to be stored in a fusebay for BIST/BISR on an ASIC or other semiconductor device. Duplicate bit correction and error correction code state machines may be included, and selectors, such as multiplexers, may be used to enable one or both types of correction. Each state machine may include an indicator, such as a “sticky bit,” that may be activated when its type of correction is encountered. The indicator(s) may be used to develop quality and yield control criteria during manufacturing test of parts including embodiments of the invention.
摘要翻译：选择性地将错误校正应用于数据，例如要存储在ASIC或其他半导体器件上的BIST / BISR的保险丝盒中的修复数据。可以包括重复的位校正和纠错码状态机，并且可以使用诸如多路复用器的选择器来实现一种或两种类型的校正。每个状态机可以包括当遇到其类型的校正时可以被激活的指示器，例如粘性位。指示器可用于在包括本发明的实施例的部件的制造测试期间开发质量和产量控制标准。

5. 发明授权

US07444564B2 Automatic bit fail mapping for embedded memories with clock multipliers 失效
标题翻译：带有时钟乘法器的嵌入式存储器的自动位失败映射
公开(公告)号：US07444564B2
公开(公告)日：2008-10-28
申请号：US10707071
申请日：2003-11-19
申请人： Darren L. Anand , Kevin W. Gorman , Michael R. Nelms
发明人： Darren L. Anand , Kevin W. Gorman , Michael R. Nelms
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/56 , G11C29/14 , G11C29/56008 , G11C2029/5604
摘要： A bit fail map circuit accurately generates a bit fail map of an embedded memory such as a DRAM by utilizing a high speed multiplied clock generated from a low-speed Automated Test Equipment (ATE) tester. The circuit communicates between the ATE tester, the embedded memory under test, Built-In Self-Test (BIST) and Built-In Redundancy Analysis (BIRA). An accurate bit fail map of an embedded DRAM memory is provided by pausing the BIST test circuitry at a point when a fail is encountered, namely a mismatch between BIST expected data and the actual data read from the array, and then shifting the bit fail data off the chip using the low-speed ATE tester clock. Thereafter, the high-speed test is resumed from point of fail by again running the BIST using the high-speed internal clock, to provide at-speed bit Fail Maps.
摘要翻译：位故障映射电路通过利用从低速自动测试设备（ATE）测试器产生的高速倍增时钟，精确地生成诸如DRAM的嵌入式存储器的位故障映射。该电路在ATE测试仪，被测嵌入式内存，内置自检（BIST）和内置冗余分析（BIRA）之间进行通信。通过在遇到失败时暂停BIST测试电路，即BIST预期数据与从阵列读取的实际数据之间的不匹配，然后移位位故障数据，提供嵌入式DRAM存储器的精确位故障映射使用低速ATE测试仪时钟关闭芯片。此后，通过使用高速内部时钟再次运行BIST，从故障点恢复高速测试，以提供高速位Fail Map。

6. 发明授权

US06956415B2 Modular DLL architecture for generating multiple timings 失效
标题翻译：用于生成多个时序的模块化DLL体系结构
公开(公告)号：US06956415B2
公开(公告)日：2005-10-18
申请号：US10707067
申请日：2003-11-19
申请人： Darren L. Anand , Kevin W. Gorman
发明人： Darren L. Anand , Kevin W. Gorman
IPC分类号： G06F1/04 , G11C7/22 , G11C11/407 , H03L7/00 , H03L7/06 , H03L7/07 , H03L7/08 , H03L7/081 , H03L7/16
CPC分类号： H03L7/07 , G11C7/22 , G11C7/222 , H03L7/0814
摘要： A modular Digital Locked Loop (DLL) architecture capable of generating a plurality of multiple phase clock signals, having particular applicability to synchronization of embedded DRAM systems with on chip timing. The architecture comprises a single core frequency locking circuit that includes a delay element with control logic and locking circuitry capable of locking the DLL system clock frequency to an external reference clock, and a plurality of secondary phase locking circuits capable of synchronizing a plurality of internal clock signals to any phase of the external reference clock.
摘要翻译：一种能够产生多个多相时钟信号的模块化数字锁定环（DLL）架构，其特别适用于具有片上定时的嵌入式DRAM系统的同步。该架构包括单核频率锁定电路，其包括具有控制逻辑的延迟元件和能够将DLL系统时钟频率锁定到外部参考时钟的锁定电路，以及能够使多个内部时钟同步的多个次级锁相电路信号到外部参考时钟的任何相位。

7. 发明授权

US08649239B2 Multi-bank random access memory structure with global and local signal buffering for improved performance 有权
标题翻译：具有全局和本地信号缓冲的多存储体随机存取存储器结构，以提高性能
公开(公告)号：US08649239B2
公开(公告)日：2014-02-11
申请号：US13479448
申请日：2012-05-24
申请人： Darren L. Anand , John A. Fifield , Mark D. Jacunski , Matthew C. Lanahan
发明人： Darren L. Anand , John A. Fifield , Mark D. Jacunski , Matthew C. Lanahan
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G11C5/025 , G11C7/10 , G11C7/1048 , G11C7/18 , G11C8/12
摘要： Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.
摘要翻译：公开了多库随机存取存储器（RAM）结构的实施例，其在全局和本地连接器级提供信号缓冲以提高性能。具体来说，逆变器被并入到全局连接器中，该连接器遍历存储体组并且从存储器控制器传送信号（例如，地址信号，控制信号和/或数据信号），并且还转换成局部的交替组连接器，其将全局连接器上的节点连接到对应的存储体组，使得由存储器控制器经由全局和本地连接器的存储器组接收的任何信号由偶数个反相器缓冲并且因此是真实的信号。在全局和本地连接器级别的信号缓冲都会导致相对较快的转换速度，较短的传播延迟和低峰值功耗，同时面积消耗量的增加也会降低。

8. 发明申请

US20080002451A1 SYSTEM AND METHOD FOR DIFFERENTIAL EFUSE SENSING WITHOUT REFERENCE FUSES 有权
标题翻译：没有参考熔丝的差分EFUSE感应系统和方法
公开(公告)号：US20080002451A1
公开(公告)日：2008-01-03
申请号：US11427849
申请日：2006-06-30
申请人： Darren L. Anand , John A. Fifield , Michael R. Ouellette
发明人： Darren L. Anand , John A. Fifield , Michael R. Ouellette
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A differential fuse sensing system includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.
摘要翻译：差分保险丝感测系统包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到熔丝支脚的第一输入节点和耦合到参考的第二节点的差分读出放大器电压。保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。

9. 发明申请

US20130315022A1 MULTI-BANK RANDOM ACCESS MEMORY STRUCTURE WITH GLOBAL AND LOCAL SIGNAL BUFFERING FOR IMPROVED PERFORMANCE 有权
标题翻译：具有全球和本地信号缓存的多银行随机存取存储器结构，用于改进性能
公开(公告)号：US20130315022A1
公开(公告)日：2013-11-28
申请号：US13479448
申请日：2012-05-24
申请人： Darren L. Anand , John A. Fifield , Mark D. Jacunski , Matthew C. Lanahan
发明人： Darren L. Anand , John A. Fifield , Mark D. Jacunski , Matthew C. Lanahan
IPC分类号： G11C8/00
CPC分类号： G11C11/4097 , G11C5/025 , G11C7/10 , G11C7/1048 , G11C7/18 , G11C8/12
摘要： Disclosed are embodiments of a multi-bank random access memory (RAM) structure that provides signal buffering at both the global and local connector level for improved performance. Specifically, inverters are incorporated into the global connector(s), which traverse groups of memory banks and which transmit signals (e.g., address signals, control signals, and/or data signals) from a memory controller, and also into alternating groups of local connectors, which connect nodes on the global connector(s) to corresponding groups of memory banks, such that any of the signals that are received by the memory banks from the memory controller via the global and local connectors are buffered by an even number of inverters and are thereby true signals. Signal buffering at both the global and local connector level results in relatively fast slews, short propagation delays, and low peak power consumption with minimal, if any, increase in area consumption.
摘要翻译：公开了多库随机存取存储器（RAM）结构的实施例，其在全局和本地连接器级提供信号缓冲以提高性能。具体来说，逆变器被并入到全局连接器中，该连接器遍历存储体组并且从存储器控制器传送信号（例如，地址信号，控制信号和/或数据信号），并且还转换成局部的交替组连接器，其将全局连接器上的节点连接到对应的存储体组，使得由存储器控制器经由全局和本地连接器的存储器组接收的任何信号由偶数个反相器缓冲并且因此是真实的信号。在全局和本地连接器级别的信号缓冲都会导致相对较快的转换速度，较短的传播延迟和低峰值功耗，同时面积消耗量的增加也会降低。

10. 发明授权

US07911820B2 Regulating electrical fuse programming current 有权
标题翻译：调节电熔丝编程电流
公开(公告)号：US07911820B2
公开(公告)日：2011-03-22
申请号：US12176543
申请日：2008-07-21
申请人： Darren L. Anand , John A. Fifield , John R. Goss
发明人： Darren L. Anand , John A. Fifield , John R. Goss
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C17/18
摘要： An apparatus for regulating eFUSE programming current includes a current control generator receiving an input reference current through a first current path of reference fuses, the input reference current proportional to a desired eFUSE programming current; a second current path including a reference programming FET and a second group of reference fuses; and a voltage comparator coupled to a gate terminal of the reference programming FET so as to adjust the gate voltage of the reference programming FET to equalize a first voltage across the first current path with a second voltage across the second current path. The gate voltage of the reference programming FET is an output of the current control generator, coupled to corresponding gates of one or more selected programming devices of an eFUSE array such that the selected programming devices source the desired eFUSE programming current to a selected eFUSE to be programmed.
摘要翻译：用于调节eFUSE编程电流的装置包括电流控制发生器，其通过参考熔丝的第一电流路径接收输入参考电流，所述输入参考电流与期望的eFUSE编程电流成比例; 包括参考编程FET和第二组参考保险丝的第二电流路径; 以及耦合到参考编程FET的栅极端子的电压比较器，以便调整参考编程FET的栅极电压，以跨越第二电流路径的第二电压来平衡跨越第一电流路径的第一电压。参考编程FET的栅极电压是电流控制发生器的输出，耦合到eFUSE阵列的一个或多个选定的编程设备的相应门，使得所选择的编程设备将所选择的eFUSE编程电流输出到所选择的eFUSE为程序。

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