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1. 发明授权

US08003511B2 Memory cell formation using ion implant isolated conductive metal oxide 失效
标题翻译：使用离子注入隔离导电金属氧化物的存储单元形成
公开(公告)号：US08003511B2
公开(公告)日：2011-08-23
申请号：US12653851
申请日：2009-12-18
申请人： Darrell Rinerson , Jonathan Bornstein , Robin Cheung , David Hansen , Steven W. Longcor , Rene Meyer , Lawrence Schloss
发明人： Darrell Rinerson , Jonathan Bornstein , Robin Cheung , David Hansen , Steven W. Longcor , Rene Meyer , Lawrence Schloss
IPC分类号： H01L21/44
CPC分类号： F01D17/26 , F04D29/563 , H01L21/02565 , H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1666
摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
摘要翻译：公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件（例如，表示存储数据的电阻状态）。

2. 发明申请

US20100159641A1 Memory cell formation using ion implant isolated conductive metal oxide 失效
标题翻译：使用离子注入隔离导电金属氧化物的存储单元形成
公开(公告)号：US20100159641A1
公开(公告)日：2010-06-24
申请号：US12653851
申请日：2009-12-18
申请人： Darrell Rinerson , Jonathan Bornstein , David Hansen , Robin Cheung , Steven W. Longcor , Rene Meyer , Lawrence Schloss
发明人： Darrell Rinerson , Jonathan Bornstein , David Hansen , Robin Cheung , Steven W. Longcor , Rene Meyer , Lawrence Schloss
IPC分类号： H01L21/34
CPC分类号： F01D17/26 , F04D29/563 , H01L21/02565 , H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1666
摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
摘要翻译：公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件（例如，表示存储数据的电阻状态）。

3. 发明授权

US08268667B2 Memory device using ion implant isolated conductive metal oxide 有权
标题翻译：使用离子注入隔离导电金属氧化物的存储器件
公开(公告)号：US08268667B2
公开(公告)日：2012-09-18
申请号：US13215895
申请日：2011-08-23
申请人： Darrell Rinerson , Robin Cheung , David Hansen , Steven Longcor , Rene Meyer , Jonathan Bornstein , Lawrence Schloss
发明人： Darrell Rinerson , Robin Cheung , David Hansen , Steven Longcor , Rene Meyer , Jonathan Bornstein , Lawrence Schloss
IPC分类号： H01L21/00
CPC分类号： F01D17/26 , F04D29/563 , H01L21/02565 , H01L27/0688 , H01L27/2409 , H01L27/2418 , H01L27/2472 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1666
摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).
摘要翻译：公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOx，LaSrCoOx，LaNiOx等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触并且形成用于将非易失性数据存储为多个的存储元件（例如，表示存储数据的电阻状态）。

4. 发明授权

US07888711B2 Continuous plane of thin-film materials for a two-terminal cross-point memory 失效
公开(公告)号：US07888711B2
公开(公告)日：2011-02-15
申请号：US12803214
申请日：2010-06-21
申请人： Robin Cheung , Darrell Rinerson , Travis Byonghyop Oh , Jonathan Bornstein , David Hansen
发明人： Robin Cheung , Darrell Rinerson , Travis Byonghyop Oh , Jonathan Bornstein , David Hansen
IPC分类号： H01L29/66
CPC分类号： H01L27/101 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/165 , Y10S257/903
摘要： A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

5. 发明授权

US07742323B2 Continuous plane of thin-film materials for a two-terminal cross-point memory 失效
标题翻译：用于两端交叉点存储器的薄膜材料的连续平面
公开(公告)号：US07742323B2
公开(公告)日：2010-06-22
申请号：US11881474
申请日：2007-07-26
申请人： Darrell Rinerson , Jonathan Bornstein , Robin Cheung , David Hansen , Travis Byonghyop Oh
发明人： Darrell Rinerson , Jonathan Bornstein , Robin Cheung , David Hansen , Travis Byonghyop Oh
IPC分类号： G11C11/00
CPC分类号： H01L27/101 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/165 , Y10S257/903
摘要： A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.
摘要翻译：公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。包层导体可以包括由铜制成的芯材料。

6. 发明授权

US07897951B2 Continuous plane of thin-film materials for a two-terminal cross-point memory 失效
公开(公告)号：US07897951B2
公开(公告)日：2011-03-01
申请号：US11881496
申请日：2007-07-26
申请人： Darrell Rinerson , Jonathan Bornstein , Robin Cheung , David Hansen , Travis Byonghyop Oh
发明人： Darrell Rinerson , Jonathan Bornstein , Robin Cheung , David Hansen , Travis Byonghyop Oh
IPC分类号： H01L29/02 , H01L29/06
CPC分类号： H01L27/101 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/165
摘要： A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.

7. 发明授权

US08237142B2 Continuous plane of thin-film materials for a two-terminal cross-point memory 有权
标题翻译：用于两端交叉点存储器的薄膜材料的连续平面
公开(公告)号：US08237142B2
公开(公告)日：2012-08-07
申请号：US12932642
申请日：2011-03-01
申请人： Robin Cheung , Jonathan Bornstein , David Hansen , Travis Byonghyop Oh , Darrell Rinerson
发明人： Robin Cheung , Jonathan Bornstein , David Hansen , Travis Byonghyop Oh , Darrell Rinerson
IPC分类号： H01L29/02 , H01L29/06
CPC分类号： H01L27/101 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/147 , H01L45/1641 , H01L45/165
摘要： A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.
摘要翻译：公开了一种包括多个基本平坦的薄膜层或多个共形薄膜层的存储器件的结构。薄膜层形成与第一和第二包覆导体电串联的存储元件，并且可操作以将数据存储为多个电导率分布。施加在第一和第二包层导体上的选择电压用于在存储器件上执行数据操作。存储器件可以可选地包括与存储元件和第一和第二包层导体串联电的非欧姆器件。为了形成存储元件，存储器件的制造不需要蚀刻多个薄膜层。存储元件可以包括具有选择性结晶的多晶部分和非晶部分的CMO层。包层导体可以包括由铜制成的芯材料。

8. 发明申请

US20110204019A1 Method of making a planar electrode 审中-公开
标题翻译：制作平面电极的方法
公开(公告)号：US20110204019A1
公开(公告)日：2011-08-25
申请号：US12927552
申请日：2010-11-15
申请人： Jonathan Bornstein , David Hansen , Steven W. Longcor
发明人： Jonathan Bornstein , David Hansen , Steven W. Longcor
IPC分类号： H05K3/00
摘要： Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.
摘要翻译：公开了使用包括表面活性剂化学品的浆料的薄膜材料的化学机械抛光（CMP），其可操作以抛光待平坦化的膜的高部分，同时防止薄膜的低部分的抛光。低部分可以在沉积膜的阶梯还原区域中。 CMP工艺可以用于形成平坦表面，在该平面上可以沉积后续的薄膜层，例如用于电极的导电材料。随后沉积的薄膜层基本上是平面的，不必使用CMP沉积。所得到的薄膜层是平面的并且具有均匀的横截面厚度，这对存储单元的记忆材料层是有利的。可以在先前的前端（FEOL）处理的基板（例如，硅晶片）上执行后端处理（BEOL），并且BEOL过程可用于制造两个 - 终端非易失性交叉点存储器阵列。

9. 发明授权

US07832090B1 Method of making a planar electrode 失效
标题翻译：制作平面电极的方法
公开(公告)号：US07832090B1
公开(公告)日：2010-11-16
申请号：US12660424
申请日：2010-02-25
申请人： Jonathan Bornstein , David Hansen , Steven W. Longcor
发明人： Jonathan Bornstein , David Hansen , Steven W. Longcor
IPC分类号： H01R43/00
CPC分类号： H01L27/24 , H01L21/3212 , H01L21/7684 , H01L21/76849 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.
摘要翻译：公开了使用包括表面活性剂化学品的浆料的薄膜材料的化学机械抛光（CMP），其可操作以抛光待平坦化的膜的高部分，同时防止薄膜的低部分的抛光。低部分可以在沉积膜的阶梯还原区域中。 CMP工艺可以用于形成平坦表面，在该平面上可以沉积后续的薄膜层，例如用于电极的导电材料。随后沉积的薄膜层基本上是平面的，不必使用CMP沉积。所得到的薄膜层是平面的并且具有均匀的横截面厚度，这对存储单元的记忆材料层是有利的。可以在先前的前端（FEOL）处理的基板（例如，硅晶片）上执行后端处理（BEOL），并且BEOL过程可用于制造两个 - 终端非易失性交叉点存储器阵列。

10. 发明授权

US08390100B2 Conductive oxide electrodes 有权
标题翻译：导电氧化物电极
公开(公告)号：US08390100B2
公开(公告)日：2013-03-05
申请号：US12653854
申请日：2009-12-18
申请人： Jonathan Bornstein
发明人： Jonathan Bornstein
IPC分类号： H01L21/44
CPC分类号： H01L45/12 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147
摘要： Conductive oxide electrodes are described, including a bi-layer barrier structure electrically coupled with an adhesion layer, and an electrode layer, wherein the bi-layer barrier structure includes a first barrier layer electrically coupled with the adhesion layer, and a second barrier layer electrically coupled with the first barrier layer and to the electrode layer. The conductive oxide electrodes and their associated layers can be fabricated BEOL above a substrate that includes active circuitry fabricated FEOL and electrically coupled with the conductive oxide electrodes through an interconnect structure that can also be fabricated FEOL. The conductive oxide electrodes can be used to electrically couple a plurality of non-volatile re-writeable memory cells with conductive array lines in a two-terminal cross-point memory array fabricated BEOL over the substrate and its active circuitry, the active circuitry configured to perform data operations on the memory array.
摘要翻译：描述了导电氧化物电极，其包括与粘合层电耦合的双层阻挡结构和电极层，其中双层阻挡结构包括与粘合层电耦合的第一阻挡层，以及第二阻挡层电与第一阻挡层和电极层耦合。导电氧化物电极及其相关层可以在包括有源电路制造的FEOL并且与导电氧化物电极电耦合通过也可以被制造的互连结构的基底上制造BEOL。导电氧化物电极可用于将多个非易失性可重写存储器单元与在衬底及其有源电路上制造的双端交叉点存储器阵列中的导电阵列线电耦合，该有源电路被配置为对存储器阵列执行数据操作。

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