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1. 发明授权

US08279912B2 Tranceiver non-linearity cancellation 有权
标题翻译： Tranceiver非线性取消
公开(公告)号：US08279912B2
公开(公告)日：2012-10-02
申请号：US11373928
申请日：2006-03-13
申请人： Dariush Dabiri , Jose Tellado , Sandeep Kumar Gupta
发明人： Dariush Dabiri , Jose Tellado , Sandeep Kumar Gupta
IPC分类号： H04B1/38 , H04B1/40 , H03K9/00
CPC分类号： H04L5/1423 , H04B3/23
摘要： Embodiments of a method and apparatus for reducing non-linear transmit signal components of a receive signal of a transceiver signal are disclosed. The method includes the transceiver simultaneously transmitting a transmit signal, and receiving the receive signal. A non-linear replica signal of non-linear transmission signal components that are created in the transceiver by a transmit signal DAC, and imposed onto the receive signal, is generated. The non-linear replica signal is subtracted from the received signal reducing the non-linear transmission signal components imposed onto the receive signal.
摘要翻译：公开了一种用于减少收发信机的接收信号的非线性发送信号分量的方法和装置的实施例。该方法包括收发机同时发送发送信号，并接收接收信号。产生通过发送信号DAC在收发器中产生且施加到接收信号上的非线性传输信号分量的非线性复制信号。从接收到的信号中减去非线性复制信号，减少施加在接收信号上的非线性传输信号分量。

2. 发明授权

US07720015B2 Receiver ADC clock delay base on echo signals 有权
标题翻译：接收器ADC时钟延迟基于回波信号
公开(公告)号：US07720015B2
公开(公告)日：2010-05-18
申请号：US11205615
申请日：2005-08-17
申请人： Sandeep Kumar Gupta , Jose Tellado
发明人： Sandeep Kumar Gupta , Jose Tellado
IPC分类号： H04B3/20
CPC分类号： H04B3/23
摘要： A device and method for a full-duplex transceiver is disclosed. The transceiver includes a transmitter DAC coupled to a transmission channel. The transmit DAC converting a digital transmission signal into an analog transmission signal. The transceiver further includes a receiver connected to the transmission channel. The receiver receives a desired signal and an echo signal, in which the echo signal includes at least a portion of the analog transmission signal. The receiver includes a receiver ADC, a programmable delay line for adjustably delaying a clock signal of the ADC, and a receiver processing circuit for adjusting the delay of the clock signal based at least in part upon the echo signal.
摘要翻译：公开了一种用于全双工收发器的装置和方法。收发器包括耦合到传输信道的发射机DAC。发送DAC将数字传输信号转换为模拟传输信号。收发机还包括连接到传输信道的接收机。接收器接收期望的信号和回波信号，其中回波信号包括模拟传输信号的至少一部分。接收器包括接收器ADC，用于可调延迟ADC的时钟信号的可编程延迟线，以及用于至少部分地基于回波信号调整时钟信号的延迟的接收机处理电路。

3. 发明授权

US07333448B2 Full duplex transceiver 有权
标题翻译：全双工收发器
公开(公告)号：US07333448B2
公开(公告)日：2008-02-19
申请号：US10699761
申请日：2003-11-03
申请人： Sandeep Kumar Gupta , Sanjay Kasturia , Jose Tellado
发明人： Sandeep Kumar Gupta , Sanjay Kasturia , Jose Tellado
IPC分类号： H04B3/20
CPC分类号： H04L25/14 , H04L5/1423
摘要： The invention includes a full duplex transceiver for transmitting and receiving communication signals. The transceiver includes 1 to N sample and hold circuits. Each sample and hold circuit receives a first signal that includes a far-end signal, and in some cases an echo signal, and in some cases alternatively or additionally cross-talk signals. The transceiver additionally includes a plurality of subtraction circuits. Each subtraction circuit receives an output of at least one of the sample and hold circuits. Each subtraction circuit subtracts at least a fraction of a replica signal from at least a fraction of the output of the at least one of the sample and hold circuits. The subtraction circuits generate an output that represent the far-end signal with substantially reduced echo and/or cross-talk interference, and is available for additional receiver processing.
摘要翻译：本发明包括用于发送和接收通信信号的全双工收发器。收发器包括1到N个采样和保持电路。每个采样和保持电路接收包括远端信号的第一信号，并且在某些情况下接收回波信号，并且在一些情况下接收或附加的串扰信号。收发器还包括多个减法电路。每个减法电路接收至少一个采样和保持电路的输出。每个减法电路从至少一个采样和保持电路的输出的至少一部分中减去副本信号的至少一部分。减法电路产生表示具有显着减少的回声和/或串扰干扰的远端信号的输出，并且可用于额外的接收机处理。

4. 发明授权

US12021029B2 Systems, methods, and apparatuses for an array of devices 有权
公开(公告)号：US12021029B2
公开(公告)日：2024-06-25
申请号：US17676761
申请日：2022-02-21
申请人： Sandeep Kumar Gupta
发明人： Sandeep Kumar Gupta
IPC分类号： G06F1/18 , H01L23/528
CPC分类号： H01L23/5286 , G06F1/189
摘要： Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i−1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M−1.

5. 发明授权

US08138839B2 Wideband CMOS gain stage 有权
标题翻译：宽带CMOS增益级
公开(公告)号：US08138839B2
公开(公告)日：2012-03-20
申请号：US11783601
申请日：2007-04-10
申请人： Sandeep Kumar Gupta , Venugopal Gopinathan
发明人： Sandeep Kumar Gupta , Venugopal Gopinathan
IPC分类号： H03F3/04
CPC分类号： H03F1/52 , H03F1/523 , H03F3/45085 , H03F3/45183 , H03F2200/447 , H03F2203/45288 , H03F2203/45292 , H03F2203/45324 , H03F2203/45336 , H03F2203/45398 , H03F2203/45696 , H03F2203/45722
摘要： A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.
摘要翻译： CMOS增益级包括偏置电路，其配置成在没有源极跟随器电路的情况下确保后续级的饱和。 CMOS增益级可选择用于制造CMOS增益级的工艺技术的电源电压大于允许的电源电压。为了保护CMOS增益级中的CMOS器件，公开了可选的漏极到体结结穿通保护电路。各种可选特征可以单独实现和/或以彼此的各种组合来实现。可选功能包括过程电压 - 温度（“PVT”）变化保护电路，其使增益相对独立于过程，电压和/或温度变化。可选功能还包括带宽增强电路。

6. 发明授权

US07205840B2 Wideband CMOS gain stage 有权
标题翻译：宽带CMOS增益级
公开(公告)号：US07205840B2
公开(公告)日：2007-04-17
申请号：US11165493
申请日：2005-06-24
申请人： Sandeep Kumar Gupta , Venugopal Gopinathan
发明人： Sandeep Kumar Gupta , Venugopal Gopinathan
IPC分类号： H03F3/45
CPC分类号： H03F1/52 , H03F1/523 , H03F3/45085 , H03F3/45183 , H03F2200/447 , H03F2203/45288 , H03F2203/45292 , H03F2203/45324 , H03F2203/45336 , H03F2203/45398 , H03F2203/45696 , H03F2203/45722
摘要： A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.
摘要翻译： CMOS增益级包括偏置电路，其配置成在没有源极跟随器电路的情况下确保后续级的饱和。 CMOS增益级可选择用于制造CMOS增益级的工艺技术的电源电压大于允许的电源电压。为了保护CMOS增益级中的CMOS器件，公开了可选的漏极到体结结穿通保护电路。各种可选特征可以单独实现和/或以彼此的各种组合来实现。可选功能包括过程电压 - 温度（“PVT”）变化保护电路，其使增益相对独立于过程，电压和/或温度变化。可选功能还包括带宽增强电路。

7. 发明授权

US06758516B1 Automotive vehicle with enhanced lateral collision intrusion resistance 有权
标题翻译：汽车车辆具有增强的侧向碰撞入侵阻力
公开(公告)号：US06758516B1
公开(公告)日：2004-07-06
申请号：US10250214
申请日：2003-06-13
申请人： Joseph Edward Abramczyk , Karthik Chitoor , Paul Culbertson , Zheng James Peng , Sandeep Kumar Gupta , Eric Layton Stratten , Herbert Yang
发明人： Joseph Edward Abramczyk , Karthik Chitoor , Paul Culbertson , Zheng James Peng , Sandeep Kumar Gupta , Eric Layton Stratten , Herbert Yang
IPC分类号： B62D2522
CPC分类号： B62D21/157 , B62D25/025
摘要： An automobile includes a door, inner and outer rocker panels, and a floor pan joined to the inner rocker panel. A structural frame extends under the body. A frame standoff member is mounted to the inner rocker panel and extends inboard to a frame rail. The frame standoff member is separated from the frame rail by a clearance gap. Once the gap is closed due to lateral deformation of the door, rocker panels, and floor pan, the frame standoff member will resist further deformation of the door and rocker panels without dynamically coupling the door or rocker panels to the frame rail during normal operation of the vehicle.
摘要翻译：汽车包括门，内外摇臂面板和连接到内摇杆面板的地板。结构框架在身体下方延伸。框架支座构件安装到内摇杆面板并且在内侧延伸到框架轨道。框架支撑构件与框架轨道间隔开间隙。一旦由于门，摇臂板和地板盘的横向变形而使间隙闭合，框架支撑构件将抵抗门和摇杆面板的进一步变形，而不会在正常操作期间将门或摇杆面板动态地联接到框架轨道机动车。

8. 发明授权

US12046601B2 Apparatuses, methods, and systems for an array of devices 有权
公开(公告)号：US12046601B2
公开(公告)日：2024-07-23
申请号：US17684072
申请日：2022-03-01
申请人： Sandeep Kumar Gupta
发明人： Sandeep Kumar Gupta
IPC分类号： H01L27/118
CPC分类号： H01L27/11807 , H01L2027/11881
摘要： Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal. For an embodiment, the Vss terminal of each of the devices in the first majority of the devices at location (i,j), is connected to the Vdd terminal of the device at location (i−1,j), wherein the potential of the Vss terminal of the each device at any location (1,j+1) is higher than the potential of the Vss terminal for another device at location (1,j) by a voltage Xj, for j=1:M−1, wherein a sum of all Xj voltages for j=1:(M−1) is greater than 0.25*VDD.

9. 发明授权

US11953963B2 Apparatuses and methods for an array of devices 有权
公开(公告)号：US11953963B2
公开(公告)日：2024-04-09
申请号：US17672686
申请日：2022-02-16
申请人： Sandeep Kumar Gupta
发明人： Sandeep Kumar Gupta
IPC分类号： G06F1/32 , G06F1/3206
CPC分类号： G06F1/3206
摘要： Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i−1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M−1.

10. 发明公开

US20230259148A1 Apparatuses and Methods for an Array of Devices 审中-公开
公开(公告)号：US20230259148A1
公开(公告)日：2023-08-17
申请号：US17672686
申请日：2022-02-16
申请人： Sandeep Kumar Gupta
发明人： Sandeep Kumar Gupta
IPC分类号： G05F1/46
CPC分类号： G05F1/46
摘要： Apparatuses, methods, and systems for power supply stacking of an array of devices are disclosed. For an embodiment, each device is specified by a location (i,j), each device includes a Vdd terminal, and a Vss terminal, at least a plurality of the devices further including at least one other V_Terz terminal. For an embodiment, the Vss terminal of the device at location (i,j), for i=2:N, j=1:M, is connected to the Vdd terminal of the device at location (i−1,j) resulting in a voltage between the Vdd and Vss terminals of at least a majority of the devices in the array to be a substantially same voltage VDD, wherein the potential of the Vss terminal of the each device at any location (i,j+1) is generated to be higher than the potential of the Vss terminal for another device at location (i,j) by a voltage Xj, for i=1:N, j=1:M−1.

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