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1. 发明授权

US06792179B2 Optical thumbtack 失效
标题翻译：光学图钉
公开(公告)号：US06792179B2
公开(公告)日：2004-09-14
申请号：US10334749
申请日：2002-12-31
申请人： Daoqiang Lu , Gilroy J. Vandentop , Steven N. Towle , Henning Braunisch
发明人： Daoqiang Lu , Gilroy J. Vandentop , Steven N. Towle , Henning Braunisch
IPC分类号： G02B632
CPC分类号： G02B6/43 , H05K1/0274 , H05K1/181
摘要： An optical or optoelectroronic component is mounted to a substrate, and an optical thumbtack is inserted into a through-hole of the substrate. The optical thumbtack is positioned to receive light from or send light to the optical or optoelectronic component and provide a conditioned, for example collimated or focused, beam. The optical thumbtack comprises a lens portion, a spacer portion, and a foot portion. Light may enter the thumbtack from either direction.
摘要翻译：将光学或光电元件安装到基板上，并将光学图钉插入基板的通孔中。光学图钉被定位成从光学或光电子部件接收光或发光，并提供经调理的例如准直或聚焦的光束。光学图钉包括透镜部分，间隔部分和脚部分。光可以从任一方向进入图钉。

2. 发明授权

US07703991B2 Flip-chip mountable optical connector for chip-to-chip optical interconnectability 失效
标题翻译：用于芯片到芯片光学互连的倒装芯片安装光学连接器
公开(公告)号：US07703991B2
公开(公告)日：2010-04-27
申请号：US11124033
申请日：2005-05-06
申请人： Daoqiang Lu , Gilroy J. Vandentop , Henning Braunisch
发明人： Daoqiang Lu , Gilroy J. Vandentop , Henning Braunisch
IPC分类号： G02B6/36
CPC分类号： G02B6/4232 , G02B6/4214 , G02B6/4292 , G02B6/43 , H01L2224/16225 , H05K1/0274 , H05K3/3436
摘要： An optical connector comprises a housing having a cavity extending there through to accept a mating connector. The connector comprises no optical components. Dummy solder bonding pads positioned on the connector allow the connector to be automated flip-chip bonded over a substrate waveguide.
摘要翻译：光学连接器包括壳体，该壳体具有在其上延伸以容纳匹配连接器的空腔。连接器不包括光学部件。定位在连接器上的虚拟焊接焊盘允许连接器在衬底波导上自动倒装芯片结合。

3. 发明申请

US20130344659A1 MICROELECTRONIC PACKAGE HAVING DIRECT CONTACT HEAT SPREADER AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：具有直接接触热交换器的微电子封装及其制造方法
公开(公告)号：US20130344659A1
公开(公告)日：2013-12-26
申请号：US13973975
申请日：2013-08-22
申请人： Daoqiang Lu , Chuan Hu , Gilroy J. Vandentop , Shriram Ramanathan , Rajashree Baskaran , Valery M. Dubin
发明人： Daoqiang Lu , Chuan Hu , Gilroy J. Vandentop , Shriram Ramanathan , Rajashree Baskaran , Valery M. Dubin
IPC分类号： H01L23/00
CPC分类号： H01L24/83 , H01L21/4871 , H01L23/3735 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/83 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/18161 , H01L2924/19106 , H01L2924/00
摘要： A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.
摘要翻译：一种制造具有直接接触散热器的微电子封装的方法，根据该方法形成的封装，根据该方法形成的模具散热器组合以及包含封装的系统。该方法包括金属化微电子管芯的背面以形成直接接触并固定到管芯背面的散热器主体，从而产生模具散热器组合。该封装包括模具散热器组合和与模具结合的衬底。

4. 发明授权

US09508675B2 Microelectronic package having direct contact heat spreader and method of manufacturing same 有权
公开(公告)号：US09508675B2
公开(公告)日：2016-11-29
申请号：US13973975
申请日：2013-08-22
申请人： Daoqiang Lu , Chuan Hu , Gilroy J. Vandentop , Shriram Ramanathan , Rajashree Baskaran , Valery M. Dubin
发明人： Daoqiang Lu , Chuan Hu , Gilroy J. Vandentop , Shriram Ramanathan , Rajashree Baskaran , Valery M. Dubin
IPC分类号： H01L23/00 , H01L21/48 , H01L23/373 , H01L21/00
CPC分类号： H01L24/83 , H01L21/4871 , H01L23/3735 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/83 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/18161 , H01L2924/19106 , H01L2924/00
摘要： A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.

5. 发明授权

US08541876B2 Microelectronic package having direct contact heat spreader and method of manufacturing same 有权
标题翻译：具有直接接触式散热器的微电子封装及其制造方法
公开(公告)号：US08541876B2
公开(公告)日：2013-09-24
申请号：US11242176
申请日：2005-09-30
申请人： Daoqiang Lu , Chuan Hu , Gilroy J. Vandentop , Shriram Ramanathan , Rajashree Baskaran , Valery M. Dubin
发明人： Daoqiang Lu , Chuan Hu , Gilroy J. Vandentop , Shriram Ramanathan , Rajashree Baskaran , Valery M. Dubin
IPC分类号： H01L23/10
CPC分类号： H01L24/83 , H01L21/4871 , H01L23/3735 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/83 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/18161 , H01L2924/19106 , H01L2924/00
摘要： A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.
摘要翻译：一种制造具有直接接触散热器的微电子封装的方法，根据该方法形成的封装，根据该方法形成的模具散热器组合以及包含封装的系统。该方法包括金属化微电子管芯的背面以形成直接接触并固定到管芯背面的散热器主体，从而产生模具散热器组合。该封装包括模具散热器组合和与模具结合的衬底。

6. 发明授权

US06001699A Highly selective etch process for submicron contacts 失效
标题翻译：亚微米接触的高选择性蚀刻工艺
公开(公告)号：US06001699A
公开(公告)日：1999-12-14
申请号：US589903
申请日：1996-01-23
申请人： Phi L. Nguyen , Mark A. Fradkin , Gilroy J. Vandentop
发明人： Phi L. Nguyen , Mark A. Fradkin , Gilroy J. Vandentop
IPC分类号： H01L21/311 , H01L21/768 , C03C15/00
CPC分类号： H01L21/76802 , H01L21/31116
摘要： A method for forming contacts with vertical sidewalls, high aspect ratios, improved salicide and photoresist etch selectivity at submicron dimensions. In one currently preferred embodiment, an opening is formed in a dual oxide layer by etching the undoped oxide layer at a first rate and then etching the doped oxide layer at a second rate. The etch process is performed in a low density parallel plate reactor. The process parameters of the etch are fixed in ranges which optimize the etch process and allow greater control over the critical dimensions of the opening. For example, the oxide layer is etched at a pressure in the range of approximately 100-300 mTorr and with an etch chemistry having a CHF.sub.3 :CF.sub.4 gas flow ratio in the range of approximately 3:1-1:1, respectively.
摘要翻译：用于在亚微米尺寸处形成具有垂直侧壁的接触的方法，高纵横比，改进的自对准硅化物和光致抗蚀剂蚀刻选择性。在一个当前优选的实施例中，通过以第一速率蚀刻未掺杂的氧化物层，然后以第二速率蚀刻掺杂的氧化物层，在双重氧化物层中形成开口。蚀刻工艺在低密度平行板反应器中进行。蚀刻的工艺参数固定在优化蚀刻工艺并允许对开口的关键尺寸的更大控制的范围内。例如，氧化物层在大约100-300mTorr的压力下蚀刻，并且蚀刻化学物质的CHF 3：CF 4气体流动比分别在大约3:1-1:1范围内。

7. 发明授权

US07063268B2 Electro-active fluid cooling system 失效
标题翻译：电动流体冷却系统
公开(公告)号：US07063268B2
公开(公告)日：2006-06-20
申请号：US10874131
申请日：2004-06-21
申请人： Gregory M. Chrysler , Gilroy J. Vandentop
发明人： Gregory M. Chrysler , Gilroy J. Vandentop
IPC分类号： G05D23/02 , F25D23/12 , F16K31/02 , F16K17/04 , H05K7/20
CPC分类号： H05K7/20272 , F04B19/24 , F04B43/06 , Y10T137/1624
摘要： Embodiments of the invention provide one or more valves in which an electroactive material acts to open or close the valves to increase efficiency of a pump, which may be a pump that uses an electroactive diaphragm to pump fluid. The valves and pump may pump fluid to cool a device in a system.
摘要翻译：本发明的实施例提供一种或多种阀，其中电活性材料用于打开或关闭阀，以提高泵的效率，泵可以是使用电活性隔膜来泵送流体的泵。阀和泵可以泵送流体以冷却系统中的装置。

8. 发明授权

US06717066B2 Electronic packages having multiple-zone interconnects and methods of manufacture 有权
标题翻译：具有多区域互连的电子封装和制造方法
公开(公告)号：US06717066B2
公开(公告)日：2004-04-06
申请号：US10004002
申请日：2001-11-30
申请人： Gilroy J. Vandentop , Yuan-Liang Li
发明人： Gilroy J. Vandentop , Yuan-Liang Li
IPC分类号： H01L2348
CPC分类号： H01L24/73 , H01L23/49827 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/81801 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/30107 , H01L2924/351 , H05K3/3436 , H05K2201/10378 , H05K2201/10659 , Y02P70/613 , Y10T29/4913 , Y10T29/49144 , Y10T29/49169 , H01L2924/00
摘要： To accommodate thermal stresses arising from different coefficients of thermal expansion (CTE) of a packaged or unpackaged die and a substrate, the package incorporates two or more different interconnect zones. A first interconnect zone, located in a central region of the die, employs a relatively stiff interconnect structure. A second interconnect zone, located near the periphery of the die, employs a relatively compliant interconnect structure. Additional interconnect zones, situated between the first and second interconnect zones and having interconnect structure with compliance qualities intermediate those of the first and second zones, can optionally be employed. In one embodiment, solder connections providing low electrical resistance are used in the first interconnect zone, and compliant connections, such as nanosprings, are used in the second interconnect zone. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system are also described.
摘要翻译：为了适应由封装的或未封装的裸片和衬底的不同热膨胀系数（CTE）产生的热应力，封装包含两个或多个不同的互连区域。位于模具的中心区域中的第一互连区域采用相对较硬的互连结构。位于模具周边附近的第二互连区采用相对顺应的互连结构。位于第一和第二互连区之间并具有与第一和第二区之间的顺应性质量的互连结构的附加互连区可以任选地被采用。在一个实施例中，在第一互连区域中使用提供低电阻的焊接连接，并且在第二互连区域中使用诸如纳米脉冲的顺应连接。还描述了制造方法以及将包装应用于电子组件，电子系统和数据处理系统。

9. 发明授权

US07826694B2 Electrical/optical integration scheme using direct copper bonding 有权
标题翻译：电/光集成方案采用直接铜接合
公开(公告)号：US07826694B2
公开(公告)日：2010-11-02
申请号：US12002274
申请日：2007-12-13
申请人： Gilroy J. Vandentop , Jun-Fei Zheng
发明人： Gilroy J. Vandentop , Jun-Fei Zheng
IPC分类号： G02B6/12 , H01L21/00
CPC分类号： H01L24/81 , H01L27/156 , H01L31/0203 , H01L31/18 , H01L33/62 , H01L2224/80895 , H01L2224/81801 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： An electro-optic semiconductor package and fabrication method provides enhanced performance. An integrated circuit (IC) having one or more IC contact pads is provided, where the IC contact pads are connected to an IC on the IC wafer. An intermediate wafer having one or more intermediate contact pads is provided, where the intermediate contact pads are connected to an electro-optic arrangement on the intermediate wafer. The method further provides for direct copper bonding the IC contact pads to adjacent intermediate contact pads such that an electro-optic semiconductor package results.
摘要翻译：电光半导体封装和制造方法提供增强的性能。提供具有一个或多个IC接触焊盘的集成电路（IC），其中IC接触焊盘连接到IC晶片上的IC。提供具有一个或多个中间接触焊盘的中间晶片，其中中间接触焊盘连接到中间晶片上的电光装置。该方法进一步提供将IC接触焊盘直接铜接合到相邻的中间接触焊盘，从而导致电光半导体封装。

10. 发明授权

US07821073B2 Patterned backside stress engineering for transistor performance optimization 有权
标题翻译：用于晶体管性能优化的图案化背侧应力工程
公开(公告)号：US07821073B2
公开(公告)日：2010-10-26
申请号：US12061935
申请日：2008-04-03
申请人： Gilroy J. Vandentop , Rajashree Baskaran
发明人： Gilroy J. Vandentop , Rajashree Baskaran
IPC分类号： H01L27/092
CPC分类号： H01L21/6835 , H01L21/823807 , H01L21/84 , H01L29/7842 , H01L2221/6834 , H01L2221/6835 , H01L2221/68363
摘要： Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance.
摘要翻译：本发明的一些实施例包括选择性地诱导与晶体管区域相反的背侧应力以优化晶体管性能。

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