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1. 发明授权

US06760793B2 Transaction credit control for serial I/O systems 失效
公开(公告)号：US06760793B2
公开(公告)日：2004-07-06
申请号：US10207449
申请日：2002-07-29
申请人： Richard A. Kelley , Danny Marvin Neal
发明人： Richard A. Kelley , Danny Marvin Neal
IPC分类号： G06F302
CPC分类号： G06F13/385
摘要： A method and implementing computer system are provided which allows for significantly improved input/output (I/O) subsystem designs in all systems which include serialized I/O transactions such as so-called Express specification systems. Transaction control methodology is implemented to improve Express design requirements for Express devices such as an Express switch, Express-PCI bridge, endpoint, and root complex. This is accomplished by utilizing improved transaction ordering and state machine and corresponding buffer design and improved flow control credit methodology which enables improved processing for controlling transactions flowing through Express devices including Express switches and Express-PCI bridges. An Express-PCI/PCIX transition bridge design is also provided, along with the flow control credit methodology and implementation within the Express-PCI/PCIX bridge design to enable efficient interfacing between Express and legacy or existing PCI/PCIX systems.

2. 发明授权

US06324612B1 Associating buffers in a bus bridge with corresponding peripheral devices to facilitate transaction merging 失效
标题翻译：将总线桥中的缓冲区与对应的外围设备相关联，以便于事务合并
公开(公告)号：US06324612B1
公开(公告)日：2001-11-27
申请号：US09210133
申请日：1998-12-10
申请人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1340
CPC分类号： G06F13/4059 , G06F13/4031
摘要： A bus bridge including a buffer pool and steering logic where the buffer pool is organized as a plurality of buffers sets including at least first and second buffer sets and the steering logic is adapted to store transactions originating with a first peripheral device in the first buffer set and transactions originating with a second peripheral device in the second buffer set. Transactions may arrive via a secondary bus, such as a PCI bus, coupled to the bus bridge. The bridge further allows relaxed transaction ordering rules compared to conventional PCI transaction ordering rules by identifying transactions by grant signals and thus allows steering of transactions from the first and second devices to first and second buffer sets respectively. The bridge is suitably adapted for combining or merging two or more transactions within each buffer set. Each buffer set preferably includes one or more buffers for temporarily storing transactions arriving from the secondary bus and bound for a primary bus. The primary bus may comprise a host bus connected to one or more processors or an additional PCI bus or other peripheral bus. The invention further contemplates a computer system including at least one processor, a bridge coupled to the processor via a host bus, and a plurality of peripheral devices including first and second peripheral devices coupled to the bridge via a secondary bus. In one embodiment, the bridge is configured to receive first and second request signals from the first and second peripheral devices respectively. The bridge preferably further includes arbitration logic for arbitrating mastership of the secondary bus in response to the request signals to produce first and second grant signals. The steering logic is suitably configured to utilize the first and second grant signals to determine the source of a subsequent transaction.
摘要翻译：一种包括缓冲池和转向逻辑的总线桥，其中所述缓冲池被组织为包括至少第一和第二缓冲器组的多个缓冲器组，并且所述转向逻辑适于将始发于第一外围设备的事务存储在所述第一缓冲器组中以及在第二缓冲器组中产生具有第二外围设备的交易。事务可以通过耦合到总线桥的辅助总线（诸如PCI总线）到达。与传统PCI事务排序规则相比，通过由授权信号识别事务并且因此允许将事务从第一和第二设备分别转向第一和第二缓冲器组，桥还允许轻松的事务排序规则。该桥适用于组合或合并每个缓冲区内的两个或多个事务。每个缓冲器组优选地包括一个或多个缓冲器，用于临时存储从次级总线到达并且被绑定到主总线的事务。主总线可以包括连接到一个或多个处理器或附加PCI总线或其他外围总线的主机总线。本发明进一步考虑了一种包括至少一个处理器，经由主机总线耦合到处理器的桥的计算机系统，以及包括通过次级总线耦合到桥接器的第一和第二外围设备的多个外围设备。在一个实施例中，桥被配置为分别从第一和第二外围设备接收第一和第二请求信号。桥接器优选地还包括用于响应于请求信号来仲裁辅助总线的主管以产生第一和第二授权信号的仲裁逻辑。转向逻辑被适当地配置为利用第一和第二授权信号来确定后续交易的来源。

3. 发明授权

US06301630B1 Interrupt response in a multiple set buffer pool bus bridge 失效
标题翻译：多组缓冲池总线桥中的中断响应
公开(公告)号：US06301630B1
公开(公告)日：2001-10-09
申请号：US09210127
申请日：1998-12-10
申请人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1300
CPC分类号： G06F13/4059
摘要： A bus bridge including a buffer pool comprised of a first and a second buffer sets. The first and second buffer sets are associated with first and second peripheral devices respectively. The bridge is configured to receive an interrupt and identify the interrupt source. A buffer set associated with the interrupt source is selected and transactions in the selected buffer set flushed prior to forwarding the interrupt to a processor. The bridge is preferably configured to identify the interrupt source by receiving a first interrupt signal from the first peripheral device and a second interrupt signal from the second peripheral device. Preferably, the bridge is configured to flush the transactions by pushing them into system memory via a primary bus such as a host bus of a processor. The invention further contemplates a system including a processor coupled to a host bus, a system memory, a bus bridge as described coupled between the host bus and a secondary bus, and first and second peripheral devices coupled to the secondary bus. Upon receiving an interrupt, the bridge is configured to identify the interrupt source, select a buffer set associated with the interrupt source, and flush posted memory write transactions in the selected buffer set, all prior to forwarding the interrupt to the processor. In one embodiment, the bridge, the first and second peripheral devices, and the secondary bus are compliant with the PCI specification. The bridge is configured in one embodiment to receive unique first and second interrupt signals from the first and second peripheral devices respectively.
摘要翻译：包括由第一和第二缓冲器组构成的缓冲池的总线桥。第一和第二缓冲器组分别与第一和第二外围设备相关联。桥接器配置为接收中断并识别中断源。选择与中断源关联的缓冲区，并将所选缓冲区中的事务刷新，然后再将中断转发给处理器。优选地，桥被配置为通过从第一外围设备接收第一中断信号和来自第二外围设备的第二中断信号来识别中断源。优选地，桥被配置为通过经由诸如处理器的主机总线的主总线将其推入系统存储器来刷新事务。本发明进一步考虑了一种系统，其包括耦合到主机总线的处理器，系统存储器，耦合在主机总线和辅助总线之间的总线桥，以及耦合到次级总线的第一和第二外围设备。在接收到中断时，桥被配置为识别中断源，选择与中断源相关联的缓冲区集合，以及在将中断转发到处理器之前清除所选缓冲区中的已发布的存储器写入事务。在一个实施例中，桥接器，第一和第二外围器件以及辅助总线符合PCI规范。在一个实施例中，桥被配置为分别从第一和第二外围设备接收唯一的第一和第二中断信号。

4. 发明授权

US06457077B1 System for executing a current information transfer request even when current information transfer request exceeds current available capacity of a transit buffer 有权
标题翻译：即使当前信息传送请求超过传送缓冲器的当前可用容量时，也执行当前信息传送请求的系统
公开(公告)号：US06457077B1
公开(公告)日：2002-09-24
申请号：US09329459
申请日：1999-06-10
申请人： Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber , Adalberto Guillermo Yanes
发明人： Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber , Adalberto Guillermo Yanes
IPC分类号： G06F1314
CPC分类号： G06F13/4059
摘要： A method and implementing system is provided in which system bridge circuits are enabled to execute, or over-commit to, transaction requests from system devices for information transfers which exceed the bridge circuit's current capacity to receive the requested information on its return from a designated target device such as system memory or another system device. The transaction request is moved along the data path to the designated target device and the requested information is returned, in an example, to the requesting device. By the time the requested information is returned to the requesting bridge circuit, a number of the holding buffers usually have been freed-up and are available to accept and pass the information to the requesting device. In an illustrated embodiment, the amount of over-commitment is programmable and the amount of over-commitment to transaction requests may be automatically adjusted to optimize the information transfer in accordance with the particular system demands and current data transfer traffic levels.
摘要翻译：提供了一种方法和实现系统，其中系统桥电路能够执行或过度提交来自用于信息传输的系统设备的事务请求，该信息传输超过桥电路的当前容量，以便在从指定目标返回时接收所请求的信息设备如系统内存或其他系统设备。交易请求沿着数据路径移动到指定的目标设备，并且所请求的信息在示例中返回到请求设备。当所请求的信息被返回到请求桥接电路时，多个保持缓冲器通常已经被释放并且可用于接受并将该信息传递给请求设备。在所示实施例中，过度承诺的量是可编程的，并且可以自动调整对交易请求的过度承诺的量，以根据特定系统需求和当前数据传输流量水平优化信息传递。

5. 发明授权

US06421756B1 Buffer assignment for bridges 有权
标题翻译：桥梁缓冲区分配
公开(公告)号：US06421756B1
公开(公告)日：2002-07-16
申请号：US09306200
申请日：1999-05-06
申请人： Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1340
CPC分类号： G06F13/4031 , G06F13/4059
摘要： A method and implementing computer system are provided in which bridge buffers are grouped together in a pool, and are dynamically assigned and unassigned to adapter devices as needed during information transfers. In an exemplary peripheral component interconnect (PCI) system embodiment, a PCI Host Bridge (PHB) is coupled to a first PCI bus and one of the devices of the first PCI bus is occupied by a PCI-PCI bridge (PPB) which couples the first PCI bus to a second PCI bus. An assignment of PHB buffers in the PHB is made relative to the number of PCI devices which are connected both directly and indirectly to the first PCI bus. Devices on both the first and second PCI busses are given approximately equal status in the buffer assignment process. Upon a completion of a data transfer to or from any one of the adapters, the freed-up buffers which were assigned to that particular adapter are dynamically reassigned to other adapters as needed to optimize use of all of the buffers in the PHB pool.
摘要翻译：提供了一种方法和实现的计算机系统，其中桥接缓冲器被组合在一起在池中，并且在信息传输期间根据需要被动态分配和未分配给适配器设备。在示例性外围组件互连（PCI）系统实施例中，PCI主机桥（PHB）被耦合到第一PCI总线，并且第一PCI总线的设备中的一个被PCI-PCI桥（PPB）占用，PCI桥PCI 第一个PCI总线到第二个PCI总线。相对于直接和间接连接到第一PCI总线的PCI设备的数量，PHB中的PHB缓冲器的分配。在第一和第二PCI总线上的设备在缓冲区分配过程中被赋予大致相等的状态。在完成到任何一个适配器的数据传输之后，分配给该特定适配器的释放缓冲区根据需要动态地重新分配给其他适配器，以优化PHB池中所有缓冲区的使用。

6. 发明授权

US06219737B1 Read request performance of a multiple set buffer pool bus bridge 失效
标题翻译：读请求性能的多集缓冲池总线桥
公开(公告)号：US06219737B1
公开(公告)日：2001-04-17
申请号：US09210134
申请日：1998-12-10
申请人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1314
CPC分类号： G06F13/4059
摘要： A bus bridge coupled between primary and secondary busses including a buffer pool with first and second buffer sets and steering logic configured to direct transactions received from first and second peripheral devices to the first and second buffer sets respectively. The bridge is configured to push posted memory write transactions posted in the first buffer set onto the primary bus ahead of and in response to a read request transaction from the first peripheral device while leaving transactions in the second buffer set unaffected. In one embodiment, the steering logic is configured to receive first and second grant signals produced by arbitration logic of the bridge. The first and second grant signals indicate mastership of the secondary bus and the source of a subsequent transaction to be received via the secondary bus. The bridge and the secondary bus are suitably compliant with the PCI protocol. The primary bus may be the host bus of a processor unit or a peripheral bus such as a PCI bus. The invention further contemplates a computer system including processor, a bus bridge as described coupled to the processor via a primary bus, a system memory, and first and second peripheral devices coupled to the bridge via a secondary bus. The bridge is configured to push posted memory write transactions stored in the first buffer set onto the primary bus ahead of a read request from the first peripheral device without affecting transactions stored in the second buffer set. The bridge is preferably configured to arbitrate mastership of the secondary bus among the peripheral devices in response to first and second request signals received by the bridge from the first and second peripheral devices respectively.
摘要翻译：耦合在主要和次要总线之间的总线桥，包括具有第一和第二缓冲器组的缓冲池和被配置为将从第一和第二外围设备接收的事务分别引导到第一和第二缓冲器组的转向逻辑。该桥被配置为在第一个缓冲器组中发布的已发布的存储器写入事务推送到主总线上，并且响应于来自第一外围设备的读取请求事务而将第二缓冲器组中的事务保持不受影响。在一个实施例中，转向逻辑被配置为接收由桥的仲裁逻辑产生的第一和第二授权信号。第一和第二授权信号指示辅助总线的主管和通过辅助总线接收的后续事务的来源。桥接器和辅助总线适用于PCI协议。主总线可以是处理器单元的主机总线或诸如PCI总线的外围总线。本发明进一步考虑包括处理器，如通过主总线耦合到处理器的总线桥，系统存储器以及通过次级总线耦合到桥的第一和第二外围设备的计算机系统。该桥被配置为在来自第一外围设备的读取请求之前将存储在第一缓冲器组中的已发布的存储器写事务推送到主总线上，而不会影响存储在第二缓冲器集中的事务。桥接器优选地被配置为响应于桥接器从第一和第二外围设备分别接收的第一和第二请求信号来仲裁外围设备中的辅助总线的掌握。

7. 发明授权

US06795107B1 Video conferencing apparatus and method therefor 有权
标题翻译：视频会议装置及其方法
公开(公告)号：US06795107B1
公开(公告)日：2004-09-21
申请号：US09353948
申请日：1999-07-15
申请人： Danny Marvin Neal , Richard A. Kelley
发明人： Danny Marvin Neal , Richard A. Kelley
IPC分类号： H04N714
CPC分类号： H04N21/4143 , H04N7/142 , H04N7/15 , H04N7/157 , H04N21/4223 , H04N21/4788
摘要： A videoconferencing apparatus and method are implemented. Each participant in the videoconference has a representation within the system as a “stick figure,” or linear frame, object similar to “stick figure” objects in the computer animation art. A participant's linear frame object is endowed with the persona of the participant by wrapping the object with an outer texture generated from a preloaded image of the participant. Small tags placed at preselected locations on each participant are detected by the videoconferencing system, and each of the participants stick figures is animated in accordance with changes in positions as revealed by the tags.
摘要翻译：实现视频会议装置和方法。视频会议中的每个参与者在系统中具有作为“棒图”或线性框架的对象，类似于计算机动画艺术中的“棒图”对象。参与者的线性框架对象通过用从参与者的预加载图像生成的外部纹理包裹对象来赋予参与者的角色。通过视频会议系统检测放置在每个参与者的预选位置的小标签，并且每个参与者粘贴的人物根据标签显示的位置变化而动画化。

8. 发明授权

US06405276B1 Selectively flushing buffered transactions in a bus bridge 有权
标题翻译：选择性地刷新总线桥中的缓冲事务
公开(公告)号：US06405276B1
公开(公告)日：2002-06-11
申请号：US09210135
申请日：1998-12-10
申请人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Wen-Tzer Thomas Chen , Richard A. Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1338
CPC分类号： G06F13/4059 , G06F13/4031
摘要： A bus bridge with a pool of buffers sets including first and second buffer sets. The bridge includes steering logic for directing transactions issued by a first peripheral device to the first buffer set and transactions issued by the second peripheral device to the second buffer set. The bus bridge is configured to pull posted memory write transactions ahead of a delayed read completion transaction in the first buffer set in response to identifying the first peripheral device as a target of a read request issued by a processor. In one embodiment, the bus bridge is further configured to receive first and second device select signals from the first and second peripheral devices respectively. In this embodiment, the device select signals indicate the target of the read request issued by the processor. The bridge is configured, in one embodiment, such that the pulling of posted memory write transactions in the first buffer set leaves transactions in all buffer sets other than the first buffer set unaffected in response to the read request. The invention further contemplates a computer system that includes a processor coupled to a system memory via a host bus and a bus bridge as described coupled between the host bus and a secondary bus. The bridge is most preferably configured such that transactions issued by the first peripheral device are stored in the first buffer set and transactions issued by the second peripheral device are stored in the second buffer set. In one embodiment, the device driver is designed to issue the load request in response to receiving an interrupt or to check status in the device. The source of the interrupt is preferably the target of the load request.
摘要翻译：具有缓冲器集合的总线桥，包括第一和第二缓冲器组。该桥包括用于将由第一外围设备发出的交易指向第一缓冲器组的转向逻辑，以及由第二外围设备向第二缓冲器组发出的事务。总线桥被配置为响应于将第一外围设备识别为由处理器发出的读取请求的目标，在第一缓冲器集合中的延迟读取完成事务之前拉动已存储的写入事务。在一个实施例中，总线桥还被配置为分别从第一和第二外围设备接收第一和第二设备选择信号。在本实施例中，设备选择信号指示由处理器发出的读取请求的目标。在一个实施例中，桥被配置为使得在第一缓冲器组中拉动已发布的存储器写入事务使得除了响应于读取请求不受影响的第一缓冲器集之外的所有缓冲器集中的事务。本发明进一步设想一种计算机系统，其包括经由主机总线和总线桥连接到系统存储器的处理器，其耦合在主机总线和辅助总线之间。该桥最优选地配置为使得由第一外围设备发出的交易存储在第一缓冲器组中，并且由第二外围设备发出的事务存储在第二缓冲器组中。在一个实施例中，设备驱动器被设计为响应于接收到中断或检查设备中的状态而发出加载请求。中断源最好是加载请求的目标。

9. 发明授权

US07165110B2 System and method for simultaneously establishing multiple connections 有权
标题翻译：同时建立多个连接的系统和方法
公开(公告)号：US07165110B2
公开(公告)日：2007-01-16
申请号：US09903725
申请日：2001-07-12
申请人： Danny Marvin Neal , Gregory Francis Pfister , Renato John Recio
发明人： Danny Marvin Neal , Gregory Francis Pfister , Renato John Recio
IPC分类号： G06F15/16 , G06F11/30 , G06F12/14 , H04L9/32 , H04L9/00
CPC分类号： H04L29/06 , H04L69/14 , H04L69/22 , Y02D50/30
摘要： A system and method for establishing multiple connections using a private data field of a communication management protocol is provided. With the present invention, a Service ID identifies a specific consumer and the private data field contains a list of connection attributes for each connection that is to be established. An active side requests a connection and the passive side replies to the connection request. The active side sends the passive side a connection establishment request. This connection establishment request includes a Service ID which identifies a passive side process associated with a service. This connection establishment request also includes communication attributes of one or more connected services and datagram services associated with the Service ID. The passive passes the connection request to a process associated with the service. If the passive side process does not wish to carry out the service, a negative reply message is returned to the active side. If the passive side process does wish to carry out the service, a positive reply is returned to the active side and the reply includes the communication attributes for the connection and unreliable services associated with the Service ID used in the connection establishment request.
摘要翻译：提供了一种使用通信管理协议的私有数据字段建立多个连接的系统和方法。利用本发明，服务ID标识特定消费者，并且专用数据字段包含要建立的每个连接的连接属性的列表。主动端请求连接，被动方回复连接请求。主动端将被动方发送连接建立请求。该连接建立请求包括识别与服务相关联的被动侧进程的服务ID。该连接建立请求还包括与服务ID相关联的一个或多个连接的服务和数据报服务的通信属性。被动将连接请求传递给与服务关联的进程。如果被动侧进程不希望执行该服务，则将一个否定的回复消息返回到主动端。如果被动侧进程确实希望执行该服务，则肯定的答复返回到主动侧，并且回复包括用于连接的通信属性和与在连接建立请求中使用的服务ID相关联的不可靠服务。

10. 发明授权

US07149220B2 System, method, and product for managing data transfers in a network 有权
公开(公告)号：US07149220B2
公开(公告)日：2006-12-12
申请号：US10132456
申请日：2002-04-25
申请人： Bruce Leroy Beukema , Thomas Anthony Gregg , Danny Marvin Neal , Renato John Recio
发明人： Bruce Leroy Beukema , Thomas Anthony Gregg , Danny Marvin Neal , Renato John Recio
IPC分类号： H04L12/56
CPC分类号： H04L29/06 , H04L49/90 , H04L69/326
摘要： A method, system, and product in a data processing system are disclosed for managing data transmitted from a first end node to a second end node included in the data processing system. A logical connection is established between the first end node and the second end node prior to transmitting data between the end nodes. An instance number is associated with this particular logical connection. The instance number is included in each packet transmitted between the end nodes while this logical connection remains established. The instance number remains constant during this logical connection. The instance number is altered, such as by incrementing it, each time a logical connection between these end nodes is reestablished. Thus, each packet is associated with a particular instance of the logical connection. When a packet is received, the instance number included in the packet may be used to determine whether the packet is a stale packet transmitted during a previous logical connection between these end nodes.

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