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1. 发明申请

US20090217229A1 Wire Structures Minimizing Hostile Neighbors and Coupling Affects 有权
标题翻译：电线结构最小化敌对邻居和耦合影响
公开(公告)号：US20090217229A1
公开(公告)日：2009-08-27
申请号：US12035506
申请日：2008-02-22
申请人： Daniel Lipetz , Joshua M. Weinberg
发明人： Daniel Lipetz , Joshua M. Weinberg
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5077 , G06F2217/82
摘要： A method for minimizing coupling capacitance between wires in a bus that is shifting by way of rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, the coupling capacitance across said bus is uniform and minimized relative to the original arrangement. Alternatively, a method for minimizing coupling capacitance between wires in a bus that is shifting by way of rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, one of said wires incurs the smallest possible amount of coupling capacitance and then the coupling capacitance across the rest of said wires in said bus gets progressively worse relative to the original arrangement.
摘要翻译：一种用于最小化总线中导线之间的耦合电容的方法，该总线通过重新排列所述总线中的所述导线的顺序而移位，使得除了所述布置中的所述第一和最后导线之外，跨所述总线的耦合电容是均匀的并且最小化相对于原来的安排。或者，一种用于使总线中的导线之间的耦合电容最小化的方法，该方法是通过重新排列所述总线中的所述导线的顺序而移位，使得除了所述布置中的所述第一和最后的导线之外，所述布线中的一个导致最小的可能耦合电容量，然后在所述总线中的所述电线的其余部分的耦合电容相对于原始布置逐渐变差。

2. 发明授权

US07962880B2 Wire structures minimizing coupling effects between wires in a bus 有权
标题翻译：电线结构使母线电线之间的耦合效应最小化
公开(公告)号：US07962880B2
公开(公告)日：2011-06-14
申请号：US12035506
申请日：2008-02-22
申请人： Daniel Lipetz , Joshua M. Weinberg
发明人： Daniel Lipetz , Joshua M. Weinberg
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5077 , G06F2217/82
摘要： A method for minimizing coupling capacitance between wires in a bus comprising shifting by rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, the coupling capacitance across said bus is uniform and minimized relative to the original arrangement. Alternatively, a method for minimizing coupling capacitance between wires in a bus comprising shifting by rearranging the order of said wires in said bus so that, aside from said first and last wires in said arrangement, one of said wires incurs the smallest possible amount of coupling capacitance and then the coupling capacitance across the rest of said wires in said bus gets progressively worse relative to the original arrangement.
摘要翻译：一种用于最小化总线中的线之间的耦合电容的方法，包括通过重新排列所述总线中的所述导线的顺序来移位，使得除了所述布置中的所述第一和最后导线之外，跨所述总线的耦合电容是均匀的并且相对于原来的安排。或者，一种用于使总线中的线之间的耦合电容最小化的方法，包括通过重新排列所述总线中的所述线的顺序来移位，使得除了所述布置中的所述第一和最后的导线之外，所述线中的一个导致最小可能量的耦合然后在所述总线中的所述电线的其余部分的耦合电容相对于原始布置逐渐变差。

3. 发明申请

US20110131266A1 Decimal Floating Point Multiplier and Design Structure 失效
标题翻译：十进制浮点乘数和设计结构
公开(公告)号：US20110131266A1
公开(公告)日：2011-06-02
申请号：US12629081
申请日：2009-12-02
申请人： Steven R. Carlough , Daniel Lipetz , Joshua M. Weinberg
发明人： Steven R. Carlough , Daniel Lipetz , Joshua M. Weinberg
IPC分类号： G06F7/52
CPC分类号： G06F7/4915 , G06F2207/4911
摘要： Several implementations and a design structure for decimal multiplication that uses a BCD 4221 encoding scheme, separate accumulation of partial products, accumulation of the partial products into a final product and conversion from and to a BCD 8421 coding scheme.
摘要翻译：使用BCD 4221编码方案的小数乘法的几种实现和设计结构，部分乘积的单独积累，部分乘积的累积到最终产品以及从BCD 8421编码方案的转换。

4. 发明申请

US20090216824A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DETERMINING REQUIRED PRECISION IN FIXED-POINT DIVIDE OPERATIONS 有权
标题翻译：方法，系统和计算机程序产品用于确定固定点操作中所需的精度
公开(公告)号：US20090216824A1
公开(公告)日：2009-08-27
申请号：US12037207
申请日：2008-02-26
申请人： Joshua M. Weinberg , Martin S. Schmookler
发明人： Joshua M. Weinberg , Martin S. Schmookler
IPC分类号： G06F7/487
CPC分类号： G06F7/535 , G06F2207/5355
摘要： A method, computer program product and a system for controlling a fixed point division operation are provided. The method includes: receiving an instruction to perform a division operation for a dividend and a divisor, the operation comprising a maximum number of iterations to produce a quotient having a maximum precision; calculating a magnitude of at least one of the dividend and the divisor; determining a quotient precision based on the magnitude; and computing a required number of iterations needed to produce the quotient precision and performing the number of iterations.
摘要翻译：提供了一种用于控制固定点分割操作的方法，计算机程序产品和系统。该方法包括：接收执行对除数和除数的除法运算的指令，所述操作包括最大迭代次数以产生具有最大精度的商; 计算至少一个股息和除数的幅度; 基于幅度确定商精度; 并计算产生商精度和执行迭代次数所需的迭代次数。

5. 发明授权

US08667258B2 High performance cache translation look-aside buffer (TLB) lookups using multiple page size prediction 失效
标题翻译：使用多页大小预测的高性能缓存翻译后备缓冲区（TLB）查找
公开(公告)号：US08667258B2
公开(公告)日：2014-03-04
申请号：US12821723
申请日：2010-06-23
申请人： Brian R. Prasky , Gregory W. Alexander , James J. Bonanno , Aaron Tsai , Joshua M. Weinberg
发明人： Brian R. Prasky , Gregory W. Alexander , James J. Bonanno , Aaron Tsai , Joshua M. Weinberg
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F9/26 , G06F9/34
CPC分类号： G06F9/3806 , G06F12/1027 , G06F2212/652 , G06F2212/654
摘要： A computer processing system method and apparatus having a processor employing an operating system (O/S) multi-task control between multiple user programs and which ensures that the programs do not interfere with each other, said computing processing system having a branch multiple page size prediction mechanism which predicts a page size along with a branch direction and a branch target of a branch for instructions of a processing pipeline, having a branch target buffer (BTB) predicting the branch target, said branch prediction mechanism storing recently used instructions close to the processor in a local cache, and having a translation look-aside buffer TLB mechanism which tracks the translation of the most recent pages and supports multiple page sizes.
摘要翻译：一种具有处理器的计算机处理系统方法和装置，所述处理器采用多个用户程序之间的操作系统（O / S）多任务控制，并确保所述程序不相互干扰，所述计算处理系统具有分支多页大小预测机构，其预测具有分支目标缓冲器（BTB）的处理流水线的指示的分支方向的分支方向和分支目标的分页目标，所述分支目标缓冲器（BTB）预测分支目标，所述分支预测机制存储最近使用的指令，处理器，并且具有跟踪最近页面的翻译并支持多个页面大小的翻译后备缓冲器TLB机制。

6. 发明申请

US20090216825A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DETECTING ERRORS IN FIXED POINT DIVISION OPERATION RESULTS 有权
标题翻译：方法，系统和计算机程序产品，用于检测固定点操作结果中的错误
公开(公告)号：US20090216825A1
公开(公告)日：2009-08-27
申请号：US12037408
申请日：2008-02-26
申请人： Joshua M. Weinberg , Martin S. Schmookler
发明人： Joshua M. Weinberg , Martin S. Schmookler
IPC分类号： G06F7/44
CPC分类号： G06F7/5375
摘要： A method, computer program product and a system for detecting errors in a result of a fixed-point division operation are provided. The method includes: receiving a result of a fixed-point division operation for a dividend and a divisor; performing a first comparison of the divisor and a remainder of the result; performing a second comparison of a sign of the dividend and a sign of the remainder; and determining whether the result is correct based on the first comparison and the second comparison.
摘要翻译：提供了一种用于检测定点分割操作的结果中的错误的方法，计算机程序产品和系统。该方法包括：接收除数和除数的定点除法运算结果; 执行除数和结果的其余部分的第一次比较; 对股息的符号和余数进行第二次比较; 以及基于所述第一比较和所述第二比较来确定所述结果是否正确。

7. 发明授权

US08745118B2 Verifying floating point square root operation results 有权
标题翻译：验证浮点平方根操作结果
公开(公告)号：US08745118B2
公开(公告)日：2014-06-03
申请号：US12036387
申请日：2008-02-25
申请人： Joshua M. Weinberg , Martin S. Schmookler
发明人： Joshua M. Weinberg , Martin S. Schmookler
IPC分类号： G06F7/552
CPC分类号： G06F7/483 , G06F7/5525
摘要： A method, system and computer program product for verifying a result of a floating point square root operation is provided. The method includes: receiving a result of a floating point square root operation for an operand; performing a comparison of a magnitude of a least significant bit (LSB) of the operand and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison.
摘要翻译：提供了用于验证浮点平方根操作的结果的方法，系统和计算机程序产品。该方法包括：接收操作数的浮点平方根操作的结果; 执行操作数的最低有效位（LSB）的大小与余数的最高有效位（MSB）的大小的比较; 以及基于所述比较来确定所述结果是否正确。

8. 发明授权

US08713084B2 Method, system and computer program product for verifying floating point divide operation results 有权
标题翻译：用于验证浮点除法运算结果的方法，系统和计算机程序产品
公开(公告)号：US08713084B2
公开(公告)日：2014-04-29
申请号：US12036397
申请日：2008-02-25
申请人： Joshua M. Weinberg , Martin S. Schmookler
发明人： Joshua M. Weinberg , Martin S. Schmookler
IPC分类号： G06F7/44
CPC分类号： G06F7/4873
摘要： A method, system and computer program product for verifying a result of a floating point division operation are provided. The method includes: receiving a result of a floating point division operation for a dividend and a divisor; performing a comparison of a magnitude of a least significant bit (LSB) of the dividend and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison.
摘要翻译：提供了用于验证浮点除法运算结果的方法，系统和计算机程序产品。该方法包括：接收分红和除数的浮点除法运算结果; 执行除数的最低有效位（LSB）的大小与余数的最高有效位（MSB）的大小的比较; 以及基于所述比较来确定所述结果是否正确。

9. 发明申请

US20110320774A1 OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE 有权
标题翻译：操作控制作为分支机构的功能
公开(公告)号：US20110320774A1
公开(公告)日：2011-12-29
申请号：US12822379
申请日：2010-06-24
申请人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
发明人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
IPC分类号： G06F9/38
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3806 , G06F9/3844 , G06F9/3857
摘要： A system for data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.
摘要翻译：一种用于数据操作数取出控制的系统包括一计算机处理器，该计算机处理器包括用于确定存储器访问操作的控制控制单元被配置为执行方法。该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。该方法还包括将尝试访问系统存储器的所选择的指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。该方法还包括基于映射执行针对所选择的指令的存储器访问操作。

10. 发明授权

US08626816B2 Method, system and computer program product for detecting errors in fixed point division operation results 有权
标题翻译：用于检测定点分割运算结果误差的方法，系统和计算机程序产品
公开(公告)号：US08626816B2
公开(公告)日：2014-01-07
申请号：US12037408
申请日：2008-02-26
申请人： Joshua M. Weinberg , Martin S. Schmookler
发明人： Joshua M. Weinberg , Martin S. Schmookler
IPC分类号： G06F7/52
CPC分类号： G06F7/5375
摘要： A method, computer program product and a system for detecting errors in a result of a fixed-point division operation are provided. The method includes: receiving a result of a fixed-point division operation for a dividend and a divisor; performing a first comparison of the divisor and a remainder of the result; performing a second comparison of a sign of the dividend and a sign of the remainder; and determining whether the result is correct based on the first comparison and the second comparison.
摘要翻译：提供了一种用于检测定点分割操作的结果中的错误的方法，计算机程序产品和系统。该方法包括：接收除数和除数的定点除法运算结果; 执行除数和结果的其余部分的第一次比较; 对股息的符号和余数进行第二次比较; 以及基于所述第一比较和所述第二比较来确定所述结果是否正确。

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