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1. 发明申请

US20140063925A1 PARALLEL PROGRAMMING MULTIPLE PHASE CHANGE MEMORY CELLS 审中-公开
标题翻译：并行编程多相变化记忆细胞
公开(公告)号：US20140063925A1
公开(公告)日：2014-03-06
申请号：US13434739
申请日：2012-03-29
申请人： Daniel J. Friedman , Seongwon Kim , Yong Liu , Bipin Rajendran
发明人： Daniel J. Friedman , Seongwon Kim , Yong Liu , Bipin Rajendran
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0085 , G11C2013/0088 , G11C2013/0092 , G11C2213/79
摘要： Embodiments of the present invention provide a device comprising a plurality of phase change memory cells, a word line, and a plurality of bit lines. Each phase change memory cell is coupled to a corresponding transistor. Each transistor is coupled to the word line. Each bit line is coupled to a phase change memory cell of the device. The device further comprises a programming circuit configured to program at least one phase change memory cell to the SET state by selectively applying a two-stage waveform to the word line and the bit lines of the device. In a first stage, a first predetermined low voltage and a first predetermined high voltage are applied at the word line and the bit lines, respectively. In a second stage, a second predetermined high voltage and a predetermined voltage with decreasing amplitude are applied at the word line and the bit lines, respectively.
摘要翻译：本发明的实施例提供一种包括多个相变存储单元，字线和多个位线的装置。每个相变存储单元耦合到相应的晶体管。每个晶体管耦合到字线。每个位线耦合到器件的相变存储器单元。该装置还包括编程电路，其被配置为通过选择性地将两级波形应用于该装置的字线和位线来将至少一个相变存储器单元编程到SET状态。在第一阶段中，分别在字线和位线处施加第一预定低电压和第一预定高电压。在第二级中，分别在字线和位线处施加具有降低幅度的第二预定高电压和预定电压。

2. 发明申请

US20120084241A1 PRODUCING SPIKE-TIMING DEPENDENT PLASTICITY IN A NEUROMORPHIC NETWORK UTILIZING PHASE CHANGE SYNAPTIC DEVICES 有权
标题翻译：在使用相位变化的同步设备的神经网络中生产依赖于时间的相对塑性
公开(公告)号：US20120084241A1
公开(公告)日：2012-04-05
申请号：US12895791
申请日：2010-09-30
申请人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
IPC分类号： G06N3/063
CPC分类号： G06N3/06 , G06N3/049 , G06N3/063 , G06N3/0635 , G06N3/08 , G11C11/54 , G11C13/0004
摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
摘要翻译：本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

3. 发明授权

US09269042B2 Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices 有权
标题翻译：使用相变突触装置在神经元网络中产生尖峰时间依赖性可塑性
公开(公告)号：US09269042B2
公开(公告)日：2016-02-23
申请号：US12895791
申请日：2010-09-30
申请人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
发明人： Daniel J. Friedman , Seongwon Kim , Chung H. Lam , Dharmendra S. Modha , Bipin Rajendran , Jose A. Tierno
IPC分类号： G06N3/063 , G06N3/04 , G11C11/54 , G11C13/00
CPC分类号： G06N3/06 , G06N3/049 , G06N3/063 , G06N3/0635 , G06N3/08 , G11C11/54 , G11C13/0004
摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.
摘要翻译：本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

4. 发明授权

US08824218B2 Compact low-power asynchronous resistor-based memory read operation and circuit 有权
标题翻译：紧凑型低功耗基于异步电阻的存储器读操作和电路
公开(公告)号：US08824218B2
公开(公告)日：2014-09-02
申请号：US13552932
申请日：2012-07-19
申请人： Seongwon Kim , Yong Liu , Bipin Rajendran
发明人： Seongwon Kim , Yong Liu , Bipin Rajendran
IPC分类号： G11C7/06
CPC分类号： G11C13/004 , G11C7/067 , G11C11/5678 , G11C13/0004
摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.
摘要翻译：紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。读出放大器读取存储单元的状态。感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器状态。

5. 发明授权

US08331164B2 Compact low-power asynchronous resistor-based memory read operation and circuit 有权
标题翻译：紧凑型低功耗基于异步电阻的存储器读操作和电路
公开(公告)号：US08331164B2
公开(公告)日：2012-12-11
申请号：US12960651
申请日：2010-12-06
申请人： Seongwon Kim , Yong Liu , Bipin Rajendran
发明人： Seongwon Kim , Yong Liu , Bipin Rajendran
IPC分类号： G11C7/06
CPC分类号： G11C13/004 , G11C7/067 , G11C11/5678 , G11C13/0004
摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.
摘要翻译：紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。读出放大器读取存储单元的状态。感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器状态。

6. 发明申请

US20120140554A1 COMPACT LOW-POWER ASYNCHRONOUS RESISTOR-BASED MEMORY READ OPERATION AND CIRCUIT 有权
标题翻译：紧凑型低功耗异步电动势记忆读取操作和电路
公开(公告)号：US20120140554A1
公开(公告)日：2012-06-07
申请号：US12960651
申请日：2010-12-06
申请人： Seongwon Kim , Yong Liu , Bipin Rajendran
发明人： Seongwon Kim , Yong Liu , Bipin Rajendran
IPC分类号： G11C11/00 , G11C7/00 , G11C7/06
CPC分类号： G11C13/004 , G11C7/067 , G11C11/5678 , G11C13/0004
摘要： A compact, low-power, asynchronous, resistor-based memory read circuit includes a memory cell having a plurality of consecutive memory states, each of said states corresponding to a respective output voltage. A sense amplifier reads the state of the memory cell. The sense amplifier includes a voltage divider configured to receive the output voltage of the memory cell and to output a settled voltage an amplifier having a voltage threshold between the settled voltages associated with two of said consecutive memory states, configured to discriminate between said two consecutive memory states.
摘要翻译：紧凑型低功率异步电阻器存储器读取电路包括具有多个连续存储器状态的存储单元，每个所述状态对应于相应的输出电压。读出放大器读取存储单元的状态。感测放大器包括分压器，其被配置为接收存储器单元的输出电压并且输出稳定电压，放大器具有在与所述连续存储器状态中的两个相关联的稳定电压之间的电压阈值，其被配置为区分所述两个连续存储器状态。

7. 发明授权

US07279949B2 Programmable delay element 有权
标题翻译：可编程延迟元件
公开(公告)号：US07279949B2
公开(公告)日：2007-10-09
申请号：US11215416
申请日：2005-08-30
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Daniel J. Friedman , Seongwon Kim , Hector Saenz , Michael A. Sperling
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Daniel J. Friedman , Seongwon Kim , Hector Saenz , Michael A. Sperling
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/133 , H03K2005/00039
摘要： Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage generator coupled to the reference current generator for generating a set of bias voltages based on the constant current generated by the reference current generator and a digitally programmable delay control input, and at least one delay element coupled to the at least one variable bias voltage generator for delaying the input signal by a constant delay which is determined by the set of bias voltages generated by the at least one variable bias voltage generator.
摘要翻译：公开了具有无毛刺操作的延迟元件和延迟线。作为示例，用于延迟输入信号的装置包括用于产生恒定电流的参考电流发生器，其中恒定电流对电源电压的变化不敏感，耦合到参考电流发生器的至少一个可变偏置电压发生器用于基于由参考电流发生器和数字可编程延迟控制输入产生的恒定电流产生一组偏置电压，以及耦合到所述至少一个可变偏置电压发生器的至少一个延迟元件，用于将输入信号延迟常数由所述至少一个可变偏置电压发生器产生的偏置电压组确定的延迟。

8. 发明授权

US08564262B2 Voltage regulator module with power gating and bypass 失效
标题翻译：电压调节器模块，带电源门控和旁路
公开(公告)号：US08564262B2
公开(公告)日：2013-10-22
申请号：US12944392
申请日：2010-11-11
申请人： Pradip Bose , Alper Buyuktosunoglu , Hans M. Jacobson , Seongwon Kim
发明人： Pradip Bose , Alper Buyuktosunoglu , Hans M. Jacobson , Seongwon Kim
IPC分类号： G05G1/56
CPC分类号： G05F1/575 , G05F1/565
摘要： Mechanisms are provided for either power gating or bypassing a voltage regulator. Responsive to receiving an asserted power gate signal to power gate the output voltage of the voltage regulator, at least one of first control circuitry power gates the output voltage of a first circuit or second control circuitry power gates the output voltage of a second circuit such that substantially no voltage to is output by the first circuit to a primary output node. Responsive to receiving an asserted bypass signal to bypass the output voltage of the voltage regulator, at least one of the first control circuitry bypasses the output voltage of the first circuit or the second control circuitry bypasses the output voltage of a second circuit such that substantially the voltage of a voltage source is output by the first circuit to the primary output node.
摘要翻译：提供电源门控或旁路电压调节器的机制。响应于接收到被断言的电源门信号以对所述电压调节器的输出电压进行电源门控，第一控制电路电源的至少一个功率门是第一电路或第二控制电路电路的输出电压门控第二电路的输出电压，使得基本上没有电压被第一电路输出到主输出节点。响应于接收断言的旁路信号以绕过电压调节器的输出电压，第一控制电路中的至少一个旁路第一电路或第二控制电路的输出电压旁路第二电路的输出电压，使得基本上电压源的电压由第一电路输出到主输出节点。

9. 发明授权

US08351166B2 Leakage sensor and switch device for deep-trench capacitor array 有权
标题翻译：泄漏传感器和开关器件用于深沟槽电容阵列
公开(公告)号：US08351166B2
公开(公告)日：2013-01-08
申请号：US12508665
申请日：2009-07-24
申请人： Howard H. Chen , Kai D. Feng , Louis L. Hsu , Seongwon Kim
发明人： Howard H. Chen , Kai D. Feng , Louis L. Hsu , Seongwon Kim
IPC分类号： H01G7/16 , G01R31/12
CPC分类号： G01R31/024 , G01R31/028
摘要： A high-density deep trench capacitor array with a plurality of leakage sensors and switch devices. Each capacitor array further comprises a plurality of sub-arrays, wherein the leakage in each sub-array is independently controlled by a sensor and switch unit. The leakage sensor comprises a current mirror, a transimpedance amplifier, a voltage comparator, and a timer. If excessive leakage current is detected, the switch unit will automatically disconnect the leaky capacitor module to reduce stand-by power and improve yield. An optional solid-state resistor can be formed on top of the deep trench capacitor array to increase the temperature and speed up the leakage screening process.
摘要翻译：一种高密度深沟槽电容阵列，具有多个漏电传感器和开关器件。每个电容器阵列还包括多个子阵列，其中每个子阵列中的泄漏由传感器和开关单元独立地控制。泄漏传感器包括电流镜，跨阻放大器，电压比较器和定时器。如果检测到过大的漏电流，开关单元将自动断开泄漏电容器模块，以降低待机功率并提高产量。可以在深沟槽电容器阵列的顶部形成可选的固态电阻器，以增加温度并加快泄漏检测过程。

10. 发明申请

US20110161682A1 PROCESSOR VOLTAGE REGULATION 有权
标题翻译：处理器电压调节
公开(公告)号：US20110161682A1
公开(公告)日：2011-06-30
申请号：US12650516
申请日：2009-12-30
申请人： Huajun Wen , Joshua D. Friedrich , Norman K. James , Seongwon Kim , John R. Ripley , Edmund J. Sprogis
发明人： Huajun Wen , Joshua D. Friedrich , Norman K. James , Seongwon Kim , John R. Ripley , Edmund J. Sprogis
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G05F1/56 , G06F1/26 , G06F1/3287 , Y02D10/171
摘要： A voltage regulator module (VRM) includes a first interface configured to couple to a first substrate interface at a first voltage. The VRM also includes a second interface configured to couple to a first processor interface at a second voltage. A first regulator module couples to the first interface and to the second interface. The first regulator module is configured to receive power at the first interface, to convert power to the second voltage, and to deliver power to the first processor interface at the second voltage. A method for providing power to a processor includes receiving power from a first substrate interface at a first voltage. The received power is regulated to generate power at a second voltage. The regulated power is provided to a processor at a first processor interface coupled to the processor. The processor interface delivers power to a logic group of a plurality of logic groups of the processor.
摘要翻译：电压调节器模块（VRM）包括被配置为以第一电压耦合到第一衬底接口的第一接口。 VRM还包括被配置为以第二电压耦合到第一处理器接口的第二接口。第一调节器模块耦合到第一接口和第二接口。第一调节器模块被配置为在第一接口处接收电力，以将功率转换为第二电压，并且以第二电压将功率输送到第一处理器接口。向处理器提供电力的方法包括以第一电压从第一基板接口接收功率。接收的功率被调节以在第二电压下产生功率。将调节的功率提供给耦合到处理器的第一处理器接口处的处理器。处理器接口向处理器的多个逻辑组的逻辑组递送电力。

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