专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06192482B1 Self-timed parallel data bus interface to direct storage devices 失效
标题翻译：自定时并行数据总线接口直接存储设备
公开(公告)号：US06192482B1
公开(公告)日：2001-02-20
申请号：US08261523
申请日：1994-06-17
申请人： Daniel Francis Casper , James Thomas Brady , Robert Stanley Capowski , Frederick John Cox , Frank David Ferraiolo , Marten Jan Halma , Benjamin Hong Wu
发明人： Daniel Francis Casper , James Thomas Brady , Robert Stanley Capowski , Frederick John Cox , Frank David Ferraiolo , Marten Jan Halma , Benjamin Hong Wu
IPC分类号： G06F104
CPC分类号： G06F13/426
摘要： An attached storage media link has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal, providing a high speed, cost effective interface to a direct access storage device.
摘要翻译：连接的存储介质链路具有自定义接口（STI），其中时钟信号将位串行数据时钟并入并行导电总线，并且时钟信号在总线的单独线路上传输。总线上每条线上的接收数据与时钟信号单独相位对齐，为直接存取存储设备提供高速，经济有效的接口。

2. 发明授权

US06185693B2 Synchronous interface for transmitting data in a system of massively parallel processors 失效
标题翻译：用于在大规模并行处理器系统中传输数据的同步接口
公开(公告)号：US06185693B2
公开(公告)日：2001-02-06
申请号：US08669667
申请日：1996-06-24
申请人： Derrick Leroy Garmire , Robert Stanley Capowski , Daniel Francis Casper , Christine Marie Desnoyers , Frank David Ferraiolo , Marten Jan Halma , Robert Frederick Stucke
发明人： Derrick Leroy Garmire , Robert Stanley Capowski , Daniel Francis Casper , Christine Marie Desnoyers , Frank David Ferraiolo , Marten Jan Halma , Robert Frederick Stucke
IPC分类号： G06F104
CPC分类号： G06F15/17375 , G06F13/4256 , G06F15/17
摘要： A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.
摘要翻译：大规模并行系统具有自定时接口（STI），其中时钟信号将位串行数据时钟并入并行导电总线，时钟信号在总线的单独线路上传输。总线上每条线上的接收数据与时钟信号单独相位对准。数字数据通过并行总线以高速传输，为并行处理系统提供可扩展的通信网络，同时消除了精确的总线长度和系统时钟速率作为关键或限制因素。

3. 发明授权

US5694612A Self-timed interface for a network of computer processors interconnected in parallel 失效
标题翻译：并行连接的计算机处理器网络的自定时接口
公开(公告)号：US5694612A
公开(公告)日：1997-12-02
申请号：US669669
申请日：1996-06-24
申请人： Derrick Leroy Garmire , Robert Stanley Capowski , Daniel Francis Casper , Christine Marie Desnoyers , Frank David Ferraiolo , Marten Jan Halma , Robert Frederick Stucke
发明人： Derrick Leroy Garmire , Robert Stanley Capowski , Daniel Francis Casper , Christine Marie Desnoyers , Frank David Ferraiolo , Marten Jan Halma , Robert Frederick Stucke
IPC分类号： G06F13/00 , G06F13/42 , G06F15/17 , G06F15/173
CPC分类号： G06F15/17375 , G06F13/4256 , G06F15/17
摘要： A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.
摘要翻译：大规模并行系统具有自定时接口（STI），其中时钟信号将位串行数据时钟并入并行导电总线，时钟信号在总线的单独线路上传输。总线上每条线上的接收数据与时钟信号单独相位对准。数字数据通过并行总线以高速传输，为并行处理系统提供可扩展的通信网络，同时消除了精确的总线长度和系统时钟速率作为关键或限制因素。

4. 发明授权

US5832047A Self timed interface 失效
公开(公告)号：US5832047A
公开(公告)日：1998-11-03
申请号：US261515
申请日：1994-06-17
申请人： Frank David Ferraiolo , Robert Stanley Capowski , Daniel Francis Casper , Richard Carroll Jordan , William Constantino Laviola
发明人： Frank David Ferraiolo , Robert Stanley Capowski , Daniel Francis Casper , Richard Carroll Jordan , William Constantino Laviola
IPC分类号： G06F13/42 , H04L7/00 , H04L7/033
CPC分类号： H04L7/0338 , G06F13/4256 , H04L7/0008
摘要： A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.

5. 发明授权

US5651033A Inter-system data communication channel comprised of parallel electrical conductors that simulates the performance of a bit serial optical communications link 失效
标题翻译：系统间数据通信通道包括模拟位串行光通信链路性能的并行电导体
公开(公告)号：US5651033A
公开(公告)日：1997-07-22
申请号：US480705
申请日：1995-06-07
申请人： Thomas Anthony Gregg , Robert Stanley Capowski , Daniel Francis Casper , Frank David Ferraiolo
发明人： Thomas Anthony Gregg , Robert Stanley Capowski , Daniel Francis Casper , Frank David Ferraiolo
IPC分类号： G06F13/42 , H04L7/00 , H04L7/02 , H04L7/033 , H04L7/04 , H04L12/56 , H04L25/14 , H04L25/49 , H04L29/06
CPC分类号： H04L29/06 , G06F13/4278 , H04L25/14 , H04L25/4908 , H04L7/041 , H04L2007/045 , H04L69/14 , H04L7/0008
摘要： A self-timed interface (STI) links two physically separated systems or nodes. A transmit state machine forms each word in a serial bit stream into a plurality of bytes and generates idle and data character sequences. Each byte is separately encoded in a run-length-limited code, along with its idle and data character sequences. Each of the plurality of bytes is transmitted on a separate conducting line along with a transmit clock signal that is also transmitted on a separate line. At the receiver, the data stream on each line is separately phase aligned with the clock, and bit aligned.
摘要翻译：自定义接口（STI）链接两个物理上分离的系统或节点。发送状态机将串行比特流中的每个单词形成多个字节，并生成空闲和数据字符序列。每个字节分别以游程长度限制的代码及其空闲和数据字符序列编码。多个字节中的每一个与分离的线路上发送的发送时钟信号一起在单独的导线上发送。在接收机上，每行上的数据流与时钟分开相位对齐，并且位对齐。

6. 发明授权

US07362697B2 Self-healing chip-to-chip interface 失效
标题翻译：自愈芯片到芯片的接口
公开(公告)号：US07362697B2
公开(公告)日：2008-04-22
申请号：US10339757
申请日：2003-01-09
申请人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
发明人： Wiren Dale Becker , Daniel Mark Dreps , Frank David Ferraiolo , Anand Haridass , Robert James Reese
IPC分类号： G01R31/08
CPC分类号： H01L22/22 , H01L2924/0002 , H01L2924/00
摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.
摘要翻译：一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。检测用于芯片的信号路径集合内的有缺陷的信号路径。信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径有缺陷的信号路径。

7. 发明授权

US06711706B2 Method and apparatus for elastic shorts testing, a hardware-assisted wire test mechanism 失效
标题翻译：弹性短裤测试方法和装置，硬件辅助线测试机构
公开(公告)号：US06711706B2
公开(公告)日：2004-03-23
申请号：US09746610
申请日：2000-12-20
申请人： Steven Michael Douskey , Frank David Ferraiolo , Michael Stephen Floyd
发明人： Steven Michael Douskey , Frank David Ferraiolo , Michael Stephen Floyd
IPC分类号： G01R3128
CPC分类号： G06F11/24 , G01R31/2812
摘要： A method, program and system for electrical shorts testing are provided. The invention comprises setting any chips to be tested to drive 0's on their drive interfaces, and setting all receive interfaces on the chips to receive 0's and log any failures. Next a single receive interface is selected for testing. A hardware shift register is associated with each drive side interface, wherein each bit of the register is connected to an off-chip driver on the interface. This hardware shift register for the selected interface is then set to all 0's, and the first bit of the shift register is loaded to a 1. The invention then performs a pause count. After this count, the 1 is shifted to the next bit in the register and another pause count is performed. This process is repeated until the 1 is walked completely through the register and all pins on the interface have been tested. The walking 1 test is then repeated for any additional interfaces that require testing. Any nets not controlled by the new Electrical Shorts Test (EST) should ideally be set to drive 1 during this walking 1 test. In addition, an inverted shorts test can be performed in which the 1 and 0 values are reversed and a walking 0 test is performed through the register, thus allowing the interfaces to be tested at both polarities. Nets not controlled by the new EST should be driven to 0 during the Inverted test.
摘要翻译：提供了一种用于电气短路测试的方法，程序和系统。本发明包括设置要测试的任何芯片在其驱动器接口上驱动0，并且设置芯片上的所有接收接口以接收0并记录任何故障。接下来，选择单个接收界面进行测试。硬件移位寄存器与每个驱动器侧接口相关联，其中寄存器的每个位都连接到接口上的片外驱动器。然后将所选接口的该硬件移位寄存器设置为全0，并且移位寄存器的第一位被加载到1.本发明然后执行暂停计数。在该计数之后，1被移位到寄存器中的下一个位，并执行另一个暂停计数。重复此过程，直到1完全通过寄存器，并且接口上的所有引脚都已经过测试。然后对需要测试的任何其他接口重复步行1测试。理想情况下，任何不受新电气短裤测试（EST）控制的网络在此步行1测试期间应设置为驱动1。此外，可以执行反转短路测试，其中1和0值相反，并且通过寄存器执行步行0测试，从而允许在两个极性下测试接口。反向测试期间，由新的EST控制的网络应该被驱动为0。

8. 发明授权

US06671753B2 Elastic interface apparatus and method therefor 有权
公开(公告)号：US06671753B2
公开(公告)日：2003-12-30
申请号：US09961506
申请日：2001-09-24
申请人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower
发明人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower
IPC分类号： G06F1300
CPC分类号： G06F5/06 , G06F2205/104 , H04L7/0008 , H04L7/02
摘要： An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

9. 发明授权

US06542999B1 System for latching first and second data on opposite edges of a first clock and outputting both data in response to a second clock 失效
标题翻译：用于在第一时钟的相对边缘上锁存第一和第二数据并响应于第二时钟输出两个数据的系统
公开(公告)号：US06542999B1
公开(公告)日：2003-04-01
申请号：US09434801
申请日：1999-11-05
申请人： Daniel Mark Dreps , Kevin Charles Gower , Frank David Ferraiolo
发明人： Daniel Mark Dreps , Kevin Charles Gower , Frank David Ferraiolo
IPC分类号： G06F112
CPC分类号： G06F5/06
摘要： An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.
摘要翻译：实现弹性接口装置和方法。弹性接口包括用于存储数据值流的多个存储单元，其中每个存储单元顺序地存储各组数据值的成员。每个数据值被存储在本地时钟的预定数量的周期内。选择电路可以耦合到存储单元以从数据流中选择相应的数据值，以存储在相应的存储单元中。与本地时钟的目标周期上的本地时钟同步地从每个存储单元顺序地输出数据。

10. 发明授权

US06442223B1 Method and system for data transfer 失效
标题翻译：数据传输方法和系统
公开(公告)号：US06442223B1
公开(公告)日：2002-08-27
申请号：US09299716
申请日：1999-04-26
申请人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower , Toru Kobayashi , Bradley David McCredie , Hideo Sawamoto
发明人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower , Toru Kobayashi , Bradley David McCredie , Hideo Sawamoto
IPC分类号： H04L700
CPC分类号： H04L25/05 , H04L7/0012 , H04L7/02 , H04L7/046
摘要： A method and system for increasing speeds of transferring data in a data transfer system which includes a data source and data sink. Both the data source and data sink include clocks which are synchronized to a common clock frequency. A buffer is provided at the data sink and this buffer is utilized to received data from the data source. A control circuit is provided at the data sink and this control circuit receives a bus clock signal from the data source. An N segment dynamic shift register is provided within the data sink which includes at least two segments. A selectable shift control is provided for passing the data through an M segment subset of the N segment shift register, where M is less than N. Additionally, the length of the M segment subset is determined by the phase of a clock within the data sink at the time which the bus clock signal from the data source is received at the data sink. By selectively passing the data through an M segment subset of the N segment shift register, the data is accessible at the data sink at a controllable predetermined time.
摘要翻译：一种用于在包括数据源和数据宿的数据传输系统中提高传输数据速度的方法和系统。数据源和数据宿均包含与公共时钟频率同步的时钟。在数据接收器处提供缓冲器，并且该缓冲器用于从数据源接收数据。在数据宿提供控制电路，该控制电路从数据源接收总线时钟信号。 N段动态移位寄存器提供在数据宿内，其包括至少两个段。提供了可选择的移位控制，用于使数据通过N段移位寄存器的M段子集，其中M小于N.另外，M段子集的长度由数据宿内的时钟的相位确定在数据接收器处接收到来自数据源的总线时钟信号的时间。通过选择性地将数据通过N段移位寄存器的M段子集，可以在可控的预定时间在数据宿处访问数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式