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    • 1. 发明授权
    • Wireless device with a non-compensated crystal oscillator
    • 带无补偿晶体振荡器的无线设备
    • US08014476B2
    • 2011-09-06
    • US11269360
    • 2005-11-07
    • Daniel F. FilipovicCharles J. PersicoChristopher C. Riddle
    • Daniel F. FilipovicCharles J. PersicoChristopher C. Riddle
    • H04L27/06
    • H04B1/38H03J7/10H03J2200/01H03J2200/10H04L27/2332H04L2027/0036H04L2027/0055H04L2027/0065H04L2027/0087
    • A wireless device achieves good performance using a crystal oscillator that is not compensated for temperature. The crystal oscillator provides a reference signal having a temperature dependent frequency error. A control unit estimates the frequency error (e.g., based on a received pilot) and provides a frequency error estimate. A clock generator generates a digital clock, which tracks chip timing, based on the reference signal and the frequency error estimate. A receiver frequency downconverts an input RF signal with a receive LO signal having the frequency error and provides an analog baseband signal. An ADC digitizes the analog baseband signal based on a sampling clock having the frequency error and provides ADC samples. A re-clocking circuit re-clocks the ADC samples based on a digital clock and provides data samples. A digital rotator frequency translates the data samples based on the frequency error estimate and provides frequency-translated samples centered near DC.
    • 无线设备使用不补偿温度的晶体振荡器实现良好的性能。 晶体振荡器提供具有温度相关频率误差的参考信号。 控制单元估计频率误差(例如,基于接收到的导频)并提供频率误差估计。 时钟发生器基于参考信号和频率误差估计器产生跟踪芯片定时的数字时钟。 接收机使用具有频率误差的接收LO信号对输入RF信号进行下变频并提供模拟基带信号。 ADC根据具有频率误差的采样时钟数字化模拟基带信号,并提供ADC采样。 重新计时电路根据数字时钟对ADC采样进行重新计时,并提供数据采样。 数字旋转器频率基于频率误差估计来转换数据样本,并提供以DC为中心的频率转换样本。
    • 2. 发明授权
    • Method and apparatus for mitigating phase noise
    • 降低相位噪声的方法和装置
    • US07912438B2
    • 2011-03-22
    • US11688314
    • 2007-03-20
    • Daniel F. FilipovicCharles J. Persico
    • Daniel F. FilipovicCharles J. Persico
    • H04B1/10H04B17/00
    • H04B15/06
    • Techniques for mitigating additional phase noise in local oscillator (LO) signals, which may be due to digital noise coupling, are described. A correction signal having an estimate of additional phase noise in an LO signal is derived. The correction signal is applied to a data signal either after downconversion or before upconversion with the LO signal to mitigate the additional phase noise. To derive the correction signal, an input signal having the additional phase noise may be obtained by downconverting a replica LO signal or based on the replica LO signal without downconversion. The input signal may be digitized and filtered to pass a single tone and suppress remaining tones. A replica signal may be derived based on the filtered signal and frequency translated to obtain a phase noise estimate signal at DC. The complex conjugate of the phase noise estimate signal may be provided as the correction signal.
    • 描述了用于减轻本地振荡器(LO)信号中的附加相位噪声的技术,这可能是由于数字噪声耦合引起的。 导出具有LO信号中附加相位噪声的估计的校正信号。 校正信号在下转换之后或在LO信号上变频之前被施加到数据信号,以减轻额外的相位噪声。 为了导出校正信号,具有附加相位噪声的输入信号可以通过下变频复制LO信号或者基于复制LO信号而不进行下变频来获得。 输入信号可以被数字化并被滤波以通过单个音调并抑制剩余音调。 可以基于经滤波的信号和频率转换复制信号,以在DC处获得相位噪声估计信号。 可以提供相位噪声估计信号的复共轭作为校正信号。
    • 3. 发明申请
    • METHOD AND APPARATUS FOR MITIGATING PHASE NOISE
    • 减少相位噪声的方法和装置
    • US20080232611A1
    • 2008-09-25
    • US11688314
    • 2007-03-20
    • Daniel F. FilipovicCharles J. Persico
    • Daniel F. FilipovicCharles J. Persico
    • H04B15/00
    • H04B15/06
    • Techniques for mitigating additional phase noise in local oscillator (LO) signals, which may be due to digital noise coupling, are described. A correction signal having an estimate of additional phase noise in an LO signal is derived. The correction signal is applied to a data signal either after downconversion or before upconversion with the LO signal to mitigate the additional phase noise. To derive the correction signal, an input signal having the additional phase noise may be obtained by downconverting a replica LO signal or based on the replica LO signal without downconversion. The input signal may be digitized and filtered to pass a single tone and suppress remaining tones. A replica signal may be derived based on the filtered signal and frequency translated to obtain a phase noise estimate signal at DC. The complex conjugate of the phase noise estimate signal may be provided as the correction signal.
    • 描述了用于减轻本地振荡器(LO)信号中的附加相位噪声的技术,这可能是由于数字噪声耦合引起的。 导出具有LO信号中附加相位噪声的估计的校正信号。 校正信号在下转换之后或在LO信号上变频之前被施加到数据信号,以减轻额外的相位噪声。 为了导出校正信号,具有附加相位噪声的输入信号可以通过下变频复制LO信号或者基于复制LO信号而不进行下变频来获得。 输入信号可以被数字化并被滤波以通过单个音调并抑制剩余音调。 可以基于经滤波的信号和频率转换复制信号,以在DC处获得相位噪声估计信号。 可以提供相位噪声估计信号的复共轭作为校正信号。
    • 5. 发明申请
    • MULTI-RATE DIGITAL PHASE LOCKED LOOP
    • 多速数字锁相环
    • US20100310031A1
    • 2010-12-09
    • US12478506
    • 2009-06-04
    • Gary John BallantyneJifeng GengDaniel F. Filipovic
    • Gary John BallantyneJifeng GengDaniel F. Filipovic
    • H03D3/24
    • H03L7/08H03C3/0941H03C3/095H03C3/0966H03L2207/50
    • A Digital Phase-Locked Loop (DPLL) involves a Time-to-Digital Converter (TDC) that receives a DCO output signal and a reference clock and outputs a first stream of digital values. Quantization noise is reduced by clocking the TDC at a high rate. Downsampling circuitry converts the first stream into a second stream. The second stream is supplied to a phase detecting summer of the DPLL such that a control portion of the DPLL can switch at a lower rate to reduce power consumption. The DPLL is therefore referred to as a multi-rate DPLL. A third stream of digital tuning words output by the control portion is upsampled before being supplied to the DCO so that the DCO can be clocked at the higher rate, thereby reducing digital images. In a receiver application, no upsampling is performed and the DCO is clocked at the lower rate, thereby further reducing power consumption.
    • 数字锁相环(DPLL)涉及一个时间数字转换器(TDC),它接收DCO输出信号和参考时钟并输出第一个数字值。 通过以较高的速率计时TDC来减少量化噪声。 下采样电路将第一流转换为第二流。 第二流被提供给DPLL的相位检测加法器,使得DPLL的控制部分可以以较低的速率切换以降低功耗。 因此,DPLL被称为多速率DPLL。 由控制部分输出的第三个数字调谐字流在被提供给DCO之前被上采样,从而可以以更高的速率计时DCO,从而减少数字图像。 在接收机应用中,不执行上采样,并且以较低的速率对DCO进行计时,从而进一步降低功耗。
    • 6. 发明申请
    • DIGITAL PHASE-LOCKED LOOP WITH TWO-POINT MODULATION USING AN ACCUMULATOR AND A PHASE-TO-DIGITAL CONVERTER
    • 使用累加器和相数转换器进行两点调制的数字锁相环
    • US20100277211A1
    • 2010-11-04
    • US12432468
    • 2009-04-29
    • Jifeng GengGary J. BallantyneDaniel F. Filipovic
    • Jifeng GengGary J. BallantyneDaniel F. Filipovic
    • H03L7/06
    • H03L7/089H03C3/0916H03C3/0941H03C3/095H03C3/0966H03L7/085
    • A digital phase-locked loop (DPLL) supporting two-point modulation is described. In one design, the DPLL includes a phase-to-digital converter and a loop filter operating in a loop, a first processing unit for a lowpass modulation path, and a second processing unit for a highpass modulation path. The first processing unit receives an input modulating signal and provides a first modulating signal to a first point inside the loop after the phase-to-digital converter and prior to the loop filter. The second processing unit receives the input modulating signal and provides a second modulating signal to a second point inside the loop after the loop filter. The first processing unit may include an accumulator that accumulates the input modulating signal to convert frequency to phase. The second processing unit may include a scaling unit that scales the input modulating signal with a variable gain.
    • 描述了支持两点调制的数字锁相环(DPLL)。 在一种设计中,DPLL包括一个相位数转换器和一个环路工作的环路滤波器,一个用于低通调制路径的第一处理单元和一个用于高通调制路径的第二处理单元。 第一处理单元接收输入调制信号,并且在相位数转换器之后并且在环路滤波器之前向环路内的第一点提供第一调制信号。 第二处理单元接收输入调制信号,并且在环路滤波器之后向环路内的第二点提供第二调制信号。 第一处理单元可以包括累积输入调制信号以将频率转换为相位的累加器。 第二处理单元可以包括用可变增益来缩放输入调制信号的缩放单元。
    • 8. 发明授权
    • Frequency synthesizers for supporting voice communication and wireless networking standards
    • 用于支持语音通信和无线网络标准的频率合成器
    • US07171182B2
    • 2007-01-30
    • US10137101
    • 2002-05-01
    • Daniel F. Filipovic
    • Daniel F. Filipovic
    • H04B1/06
    • H03L7/16H03B21/01H04B1/406
    • Techniques are described that facilitate the generation of different waveforms at different frequencies required for transmission and reception of wireless voice signals and wireless data signals. For example, a technique may include generating a first waveform in a wireless communication device using a frequency synthesizer, wherein the first waveform has a frequency associated with a voice communication standard, and generating a second waveform in the wireless communication device using the same frequency synthesizer, wherein the second waveform has a frequency associated with a wireless networking standard. In this manner, a wireless communication device can be improved and possibly simplified.
    • 描述了促进在发送和接收无线语音信号和无线数据信号所需的不同频率下生成不同波形的技术。 例如,技术可以包括使用频率合成器在无线通信设备中生成第一波形,其中第一波形具有与语音通信标准相关联的频率,以及使用相同的频率合成器在无线通信设备中生成第二波形 ,其中所述第二波形具有与无线联网标准相关联的频率。 以这种方式,可以改进和可能地简化无线通信设备。