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1. 发明授权

US5548791A Input/output control system with plural channel paths to I/O devices 失效
标题翻译： I / O控制系统，用于基于其状态和其相关联的信道队列的可用时隙选择性地将工作分配给可用信道。
公开(公告)号：US5548791A
公开(公告)日：1996-08-20
申请号：US279581
申请日：1994-07-25
申请人： Daniel F. Casper , Steven G. Glassen , Marten J. Halma , Sandra K. Ryan
发明人： Daniel F. Casper , Steven G. Glassen , Marten J. Halma , Sandra K. Ryan
IPC分类号： G06F13/12 , G06F13/14
CPC分类号： G06F13/122
摘要： A data processing system includes a host processor and host memory means. The processor interacts with a plurality of peripheral units through an I/O system that includes a plurality of channels, one or more I/O processors (IOP's), and control data in a system area of the host memory means. Each channel has an associated busy bit in a vector, and is provided with a one position queue for dispatching work to the channel. Each queue has a bit in a vector indicating its full or empty status. A very efficient algorithm for the assignment of work for peripherals by the IOP's is provided in a system that provides for multiple paths through multiple channels between the host and a particular peripheral using the busy vector and queue vector.
摘要翻译：数据处理系统包括主机处理器和主机存储器装置。处理器通过包括多个信道，一个或多个I / O处理器（IOP）的I / O系统和主机存储器装置的系统区域中的控制数据与多个外围设备进行交互。每个通道在向量中都有一个相关联的忙位，并且具有一个位置队列，用于将工作调度到通道。每个队列都有一个向量中的位，表示其全部或空的状态。在通过忙向量和队列向量提供主机与特定外设之间的多个通道的多个路径的系统中提供了用于由IOP为外围设备分配工作的非常有效的算法。

2. 发明授权

US5522088A Shared channel subsystem has a self timed interface using a received clock signal to individually phase align bits received from a parallel bus 失效
标题翻译：共享信道子系统具有使用接收到的时钟信号的自定时接口，以对从并行总线接收的位进行单独的相位对准
公开(公告)号：US5522088A
公开(公告)日：1996-05-28
申请号：US261641
申请日：1994-06-17
申请人： Marten J. Halma , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , Martin W. Sachs
发明人： Marten J. Halma , Robert S. Capowski , Daniel F. Casper , Frank D. Ferraiolo , Martin W. Sachs
IPC分类号： G06F13/40 , G06F13/42 , G06F13/00
CPC分类号： G06F13/4022 , G06F13/405
摘要： A shared channel subsystem has an input-output element for coupling each of a plurality of input-output controllers to each of a plurality of processor nodes by means of a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal, providing a cost effective, modular input/output element.
摘要翻译：共享信道子系统具有用于通过自定义接口（STI）将多个输入 - 输出控制器中的每一个耦合到多个处理器节点中的每一个的输入 - 输出元件，其中时钟信号将位串行数据时钟并行的导电总线，并且时钟信号在总线的单独线路上传输。总线上每条线上的接收数据与时钟信号单独相位对齐，提供了一个经济有效的模块化输入/输出元件。

3. 发明授权

US5513377A Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus 失效
标题翻译：输入输出元件具有使用接收的时钟信号的自定时接口，以对从并行总线接收的单独的相位对准位
公开(公告)号：US5513377A
公开(公告)日：1996-04-30
申请号：US261561
申请日：1994-06-17
申请人： Robert S. Capowski , Daniel F. Casper , Frederick J. Cox , Frank D. Ferraiolo , Marten J. Halma
发明人： Robert S. Capowski , Daniel F. Casper , Frederick J. Cox , Frank D. Ferraiolo , Marten J. Halma
IPC分类号： H04L29/00 , G06F13/42 , H04L7/00 , G06F13/00
CPC分类号： G06F13/423
摘要： An enhanced input-output element has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal to provide a cost effective, modular, broadband, input/output element that can serve economically two channels and is modularly scalable to serve several hundred channels.
摘要翻译：增强的输入 - 输出元件具有自定时接口（STI），其中时钟信号将位串行数据时钟并入并行导电总线，时钟信号在总线的单独线路上传输。总线上每条线上的接收数据与时钟信号单独相位对准，以提供经济有效的模块化宽带输入/输出元件，可以经济地服务于两个通道，并可模块化地扩展以提供数百个通道。

4. 发明授权

US06345327B1 Queuing method and apparatus for providing direct data processing access using a queued direct input-output device 有权
标题翻译：使用排队的直接输入 - 输出设备提供直接数据处理访问的排队方法和装置
公开(公告)号：US06345327B1
公开(公告)日：2002-02-05
申请号：US09253247
申请日：1999-02-19
申请人： Michael E. Baskey , Frank W. Brice, Jr. , Steven G. Glassen , Eugene P. Hefferon , Bruce H. Ratcliff , Arthur J. Stagg , Stephen R. Valley , Daniel F. Casper , Allan S. Meritt , Anthony R. Sager , Donald W. Schmidt
发明人： Michael E. Baskey , Frank W. Brice, Jr. , Steven G. Glassen , Eugene P. Hefferon , Bruce H. Ratcliff , Arthur J. Stagg , Stephen R. Valley , Daniel F. Casper , Allan S. Meritt , Anthony R. Sager , Donald W. Schmidt
IPC分类号： G06F300
CPC分类号： H04L49/90
摘要： A queuing method and apparatus for transfer or incoming and outgoing data in a network environment having a main storage is presented. A plurality of queue sets are provided in the main storage with at least one or more sets being dedicated for input and output. The queues can share access to a plurality of devices in the network across a plurality of communication stacks. Various network resources are mapped to the queues in order to facilitate resource allocation and dynamic configuration by providing initialization of a plurality of configuration parameters. In this way dynamic expanding and contracting of the number of queues in each set as dictated by traffic patterns and feedback indicators is provided.
摘要翻译：提出了一种在具有主存储器的网络环境中用于传送或传出和传出数据的排队方法和装置。在主存储器中提供多个队列集合，其中至少一个或多个集合专用于输入和输出。队列可以跨多个通信栈共享对网络中的多个设备的访问。通过提供多个配置参数的初始化，将各种网络资源映射到队列以便于资源分配和动态配置。以这种方式，提供了由流量模式和反馈指示符指示的每组中的队列数量的动态扩展和收缩。

5. 发明授权

US06345325B1 Method and apparatus for ensuring accurate and timely processing of data using a queued direct input-output device 有权
标题翻译：使用排队的直接输入输出设备确保数据的准确和及时处理的方法和装置
公开(公告)号：US06345325B1
公开(公告)日：2002-02-05
申请号：US09252728
申请日：1999-02-19
申请人： Michael E. Baskey , Frank W. Brice, Jr. , Daniel F. Casper , Janet R. Easton , Steven G. Glassen , Eugene P. Hefferon , Bruce H. Ratcliff , Arthur J. Stagg , Leslie W. Wyman , Anthony R. Sager
发明人： Michael E. Baskey , Frank W. Brice, Jr. , Daniel F. Casper , Janet R. Easton , Steven G. Glassen , Eugene P. Hefferon , Bruce H. Ratcliff , Arthur J. Stagg , Leslie W. Wyman , Anthony R. Sager
IPC分类号： G06F1300
CPC分类号： H04L25/05
摘要： A method and an apparatus for timely and accurate processing of data in a network computing environment controlled by a running program and having a queuing mechanism established in a main storage. The main storage is in processing communication with an interface element having one or more adapters. At least one set of queues in the queuing mechanism is designated for input and another set for output. A signal adapter instruction can be issued to provide initiative to check content of any or all queues in the mechanism. With the help of the signal adapter an initiate-output can be specified when appropriate and the associated adapter can then asynchronously process the input or the output queues. A synchronize option is also available to signal the associated data queues to update all entries in order to render them current as observed by both the adapter and the controlling running program.
摘要翻译：一种用于在由运行程序控制并具有在主存储器中建立的排队机制的网络计算环境中及时准确地处理数据的方法和装置。主存储器正在处理与具有一个或多个适配器的接口元件的通信。排队机制中至少有一组队列被指定用于输入，另一组用于输出。可以发出信号适配器指令来提供主动检查机构中任何或所有队列的内容。在信号适配器的帮助下，可以在适当的时候指定启动输出，然后关联的适配器可以异步处理输入或输出队列。同步选项也可用于发信号通知相关联的数据队列来更新所有条目，以便将它们呈现为适配器和控制运行程序所观察到的当前状态。

6. 发明授权

US07656789B2 Method, system and storage medium for redundant input/output access 有权
标题翻译：用于冗余输入/输出访问的方法，系统和存储介质
公开(公告)号：US07656789B2
公开(公告)日：2010-02-02
申请号：US11092033
申请日：2005-03-29
申请人： Luiz C. Alves , Daniel F. Casper , Steven G. Glassen , Daniel J. Stigliani, Jr.
发明人： Luiz C. Alves , Daniel F. Casper , Steven G. Glassen , Daniel J. Stigliani, Jr.
IPC分类号： H04L12/26
CPC分类号： H04L1/22
摘要： A system, method and storage medium for providing redundant I/O access between a plurality of interconnected processor nodes and I/O resources. The method includes determining whether a primary path between the interconnected processor nodes and the I/O resources is operational, where the primary path includes a first processor node and a primary multiplexer. If the primary path is operational, the transactions are routed via the primary path. If the primary path is not operational, the transactions are routed between the interconnected processor nodes and the I/O resources via an alternate path that includes a second processor node and an alternate multiplexer.
摘要翻译：一种用于在多个互连的处理器节点和I / O资源之间提供冗余I / O访问的系统，方法和存储介质。该方法包括确定互连处理器节点和I / O资源之间的主路径是否可操作，其中主路径包括第一处理器节点和主多路复用器。如果主路径可操作，则通过主路径路由事务。如果主路径不可操作，则经由包括第二处理器节点和替代多路复用器的备用路径在互连的处理器节点和I / O资源之间路由事务。

7. 发明授权

US06397350B1 Method of providing direct data processing access using a queued direct input-output device 有权
标题翻译：使用排队的直接输入 - 输出设备提供直接数据处理访问的方法
公开(公告)号：US06397350B1
公开(公告)日：2002-05-28
申请号：US09253246
申请日：1999-02-19
申请人： Michael E. Baskey , Steven G. Glassen , Eugene P. Hefferon , Bruce H. Ratcliff , Arthur J. Stagg , Stephen R. Valley , Daniel F. Casper , Allan S. Meritt , Anthony R. Sager , Donald W. Schmidt
发明人： Michael E. Baskey , Steven G. Glassen , Eugene P. Hefferon , Bruce H. Ratcliff , Arthur J. Stagg , Stephen R. Valley , Daniel F. Casper , Allan S. Meritt , Anthony R. Sager , Donald W. Schmidt
IPC分类号： G06F1100
CPC分类号： G06F3/061 , G06F3/0656 , G06F3/0683
摘要： A method of providing direct data processing access in a network computing system environment. The system environment has a main storage which can be connected to one or more application servers and is in processing communication with an interface element. The interface element has at least one adapter and can be connected to one or more application user(s). One or more queues are established in the main storage that can handle data without causing interrupts in the running programs. Incoming data is received using the adapter and as data is received or modified, the status of the network computing system will be updated to reflect the new data or change. Data is then processed in the main storage after interrogating the multiple existing queues in the main storage and forwarding them in turn to their appropriate destination or application server after a determination has been made by interrogating these queues.
摘要翻译：一种在网络计算系统环境中提供直接数据处理访问的方法。系统环境具有可以连接到一个或多个应用服务器并正在处理与接口元件的通信的主存储器。接口元件具有至少一个适配器并且可以连接到一个或多个应用用户。在主存储器中建立一个或多个队列，可以处理数据，而不会导致正在运行的程序中断。使用适配器接收传入数据，并且随着数据被接收或修改，网络计算系统的状态将被更新以反映新的数据或改变。然后在主存储器中询问多个现有队列之后，在主存储器中处理数据，并且在通过询问这些队列进行确定之后将它们依次转发到其适当的目的地或应用服务器。

8. 发明授权

US06345326B1 Computer program device and product for timely processing of data using a queued direct input-output device 有权
标题翻译：计算机程序设备和产品，用于使用排队的直接输入输出设备及时处理数据
公开(公告)号：US06345326B1
公开(公告)日：2002-02-05
申请号：US09252730
申请日：1999-02-19
申请人： Michael E. Baskey , Frank W. Brice , Daniel F. Casper , Janet R. Easton , Steven G. Glassen , Eugene P. Hefferon , Bruce H. Ratcliff , Arthur J. Stagg , Leslie W. Wyman
发明人： Michael E. Baskey , Frank W. Brice , Daniel F. Casper , Janet R. Easton , Steven G. Glassen , Eugene P. Hefferon , Bruce H. Ratcliff , Arthur J. Stagg , Leslie W. Wyman
IPC分类号： G06F1300
CPC分类号： H04L25/05
摘要： A computer program device and product is provided for timely processing of data. The computer program device comprises a program storage device readable by a digital processing apparatus and a program means including instructions executable by the digital processing apparatus by designating at least one set of queues in the queuing mechanism as input queues and another as output queues; issuing a signal adapter instruction to provide initiative to check content of any or all queues in the queuing mechanism; specifying initiate-output or initiate-input appropriately by means of said signal adapter instruction to cause associated adapter to asynchronously process said output or input queues; and causing synchronization by means of said signal adapter instruction by signaling the associated data queues to update all entries in order to render them current. The computer program product is for use with a computer system and has a main storage in processing communication with an interface element having adapters for storing a queuing mechanism storing data. It comprises of a data storage device including a computer usable medium having computer readable program means for ensuring proper and timely processing of data, for dedicating at least one set of queues of the queuing mechanism as input queues and another set as output queues and for generating a signal adapter instruction designated to provide initiative to check content of any or all queues in said queuing mechanism.
摘要翻译：提供计算机程序设备和产品以及时处理数据。计算机程序设备包括可由数字处理设备读取的程序存储设备和包括可由数字处理设备执行的指令的程序设备，通过将排队机构中的至少一组队列指定为输入队列，另一个作为输出队列; 发出信号适配器指令，提供主动检查排队机构中任何或所有队列的内容; 通过所述信号适配器指令适当地指定启动输出或启动输入，以使相关联的适配器异步地处理所述输出或输入队列; 并通过所述信号适配器指令通过发信号通知相关的数据队列来更新所有条目以使其成为当前状态，从而进行同步。计算机程序产品用于计算机系统，并且具有处理与具有用于存储存储数据的排队机构的适配器的接口元件的通信的主存储器。它包括数据存储装置，包括具有计算机可读程序装置的计算机可用介质的计算机可用介质，用于确保适当和及时地处理数据，用于将排队机构的至少一组队列作为输入队列，另一组作为输出队列，并用于生成指定用于提供主动检查所述排队机构中的任何或所有队列的内容的信号适配器指令。

9. 发明授权

US09052837B2 Processing communication data in a ships passing condition 有权
标题翻译：处理船舶通行条件下的通信数据
公开(公告)号：US09052837B2
公开(公告)日：2015-06-09
申请号：US12031182
申请日：2008-02-14
申请人： Catherine C. Huang , Daniel F. Casper , John R. Flanagan , Roger G. Hathorn , Matthew J. Kalos , Louis W. Rcci
发明人： Catherine C. Huang , Daniel F. Casper , John R. Flanagan , Roger G. Hathorn , Matthew J. Kalos , Louis W. Rcci
IPC分类号： G06F3/00 , G06F3/06
CPC分类号： G06F13/4027 , G06F3/0607 , G06F3/0619 , G06F3/0659 , G06F3/0661 , G06F3/0689 , G06F13/28
摘要： Articles of manufacture, apparatuses, and methods for processing communications between a control unit and a channel subsystem in an input/output processing system are disclosed. Embodiments of the invention include an article of manufacture including at least one computer usable medium having computer readable program code logic to processing communications between a control unit and a channel subsystem in an input/output processing system. The computer readable program code logic performs a method including: sending a message in a first mode from the control unit to the channel subsystem; receiving a command in a second mode from the channel subsystem at the control unit; determining whether the command is responsive to the message; and responsive to the command being not responsive to the message, determining whether to perform one of i) executing the command and ii) terminating the command.
摘要翻译：公开了用于在输入/输出处理系统中处理控制单元和通道子系统之间的通信的制造，设备和方法。本发明的实施例包括一种制品，其包括具有计算机可读程序代码逻辑的至少一个计算机可用介质，以在输入/输出处理系统中处理控制单元和通道子系统之间的通信。计算机可读程序代码逻辑执行一种方法，包括：以第一模式从控制单元向通道子系统发送消息; 在所述控制单元处从所述通道子系统接收第二模式的命令; 确定所述命令是否响应于所述消息; 并且响应于所述命令不响应所述消息，确定是否执行i）执行所述命令和ii）终止所述命令之一。

10. 发明授权

US08677027B2 Fibre channel input/output data routing system and method 失效
标题翻译：光纤通道输入/输出数据路由系统及方法
公开(公告)号：US08677027B2
公开(公告)日：2014-03-18
申请号：US13150545
申请日：2011-06-01
申请人： Clinton E. Bubb , Daniel F. Casper , John R. Flanagan
发明人： Clinton E. Bubb , Daniel F. Casper , John R. Flanagan
IPC分类号： G06F3/00 , G06F5/00 , G06F13/00
CPC分类号： G06F13/385
摘要： A computer program product for performing input/output (I/O) processing is configured for performing a method including: obtaining information relating to an I/O operation at a channel subsystem; generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a field for storing header information; generating an address control structure specifying a location in the local channel memory of a corresponding ACW; receiving a data transfer request from a network interface that includes the address control structure; responsive to an input data request, routing the data to at least one host memory location specified by the corresponding ACW and storing header information in the corresponding ACW; and responsive to an output data request, routing the data from a host memory location specified by the ACW to the network interface and appending header information to the data.
摘要翻译：用于执行输入/输出（I / O）处理的计算机程序产品被配置为执行一种方法，包括：获得与通道子系统上的I / O操作有关的信息; 在本地信道存储器中生成和存储指定用于数据传输的一个或多个主机存储器位置的至少一个地址控制字（ACW），并且包括用于存储头信息的字段; 产生指定相应ACW的本地信道存储器中的位置的地址控制结构; 从包括所述地址控制结构的网络接口接收数据传输请求; 响应于输入数据请求，将数据路由到由相应ACW指定的至少一个主机存储器位置，并将标题信息存储在相应的ACW中; 并且响应于输出数据请求，将数据从由ACW指定的主机存储器位置路由到网络接口，并将标题信息附加到数据。

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