专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07500068B1 Method and system for managing memory in a multiprocessor system 有权
标题翻译：用于管理多处理器系统中的存储器的方法和系统
公开(公告)号：US07500068B1
公开(公告)日：2009-03-03
申请号：US11426538
申请日：2006-06-26
申请人： Daniel E. Lenoski , Jeffrey S. Kuskin , William A. Huffman , Michael S. Woodacre
发明人： Daniel E. Lenoski , Jeffrey S. Kuskin , William A. Huffman , Michael S. Woodacre
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F15/167
CPC分类号： G06F12/0817 , G06F12/0813
摘要： A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.
摘要翻译：用于管理多处理器系统中的存储器的方法和系统包括在多处理器系统的系统相干域内定义多个处理器相干域。处理器相干域各自包括多个处理器和处理器存储器。每个处理器一致性域的处理器存储器中的数据的共享访问仅提供给处理器相干域内的多处理器系统的元件。每个处理器相干域的处理器存储器中的数据的非共享访问被提供给处理器相干域内部和外部的多处理器系统的元件。

2. 发明授权

US07069306B1 Providing shared and non-shared access to memory in a system with plural processor coherence domains 有权
标题翻译：在具有多个处理器相干域的系统中提供对存储器的共享和非共享访问
公开(公告)号：US07069306B1
公开(公告)日：2006-06-27
申请号：US09910591
申请日：2001-07-20
申请人： Daniel E. Lenoski , Jeffrey S. Kuskin , William A. Huffman , Michael S Woodacre
发明人： Daniel E. Lenoski , Jeffrey S. Kuskin , William A. Huffman , Michael S Woodacre
IPC分类号： G06F15/16 , G06F12/08
CPC分类号： G06F12/0817 , G06F12/0813
摘要： A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.
摘要翻译：用于管理多处理器系统中的存储器的方法和系统包括在多处理器系统的系统相干域内定义多个处理器相干域。处理器相干域各自包括多个处理器和处理器存储器。每个处理器一致性域的处理器存储器中的数据的共享访问仅提供给处理器相干域内的多处理器系统的元件。每个处理器相干域的处理器存储器中的数据的非共享访问被提供给处理器相干域内部和外部的多处理器系统的元件。

3. 发明授权

US06795900B1 Method and system for storing data at input/output (I/O) interfaces for a multiprocessor system 有权
标题翻译：用于在多处理器系统的输入/输出（I / O）接口处存储数据的方法和系统
公开(公告)号：US06795900B1
公开(公告)日：2004-09-21
申请号：US09910363
申请日：2001-07-20
申请人： Steven C. Miller , Jeffrey S. Kuskin , William A. Huffman , Gregory M. Thorson
发明人： Steven C. Miller , Jeffrey S. Kuskin , William A. Huffman , Gregory M. Thorson
IPC分类号： G06F1200
CPC分类号： G06F12/0817 , G06F2212/2542 , G06F2212/621
摘要： A multiprocessor system and method includes a processing sub-system including a plurality of processors in a processor memory system. A network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces each operable to couple a peripheral device to the multiprocessor system. The I/O interfaces each include a local memory operable to store exclusive read-only copies of data from the processor memory system for use by a corresponding peripheral device.
摘要翻译：多处理器系统和方法包括在处理器存储器系统中包括多个处理器的处理子系统。网络可操作以将处理子系统耦合到输入/输出（I / O）子系统。 I / O子系统包括多个I / O接口，每个I / O接口可操作以将外围设备耦合到多处理器系统。 I / O接口各自包括本地存储器，其可操作以存储来自处理器存储器系统的数据的专用只读副本以供对应的外围设备使用。

4. 发明授权

US06718442B1 Method and system for using high count invalidate acknowledgements in distributed shared memory systems 有权
标题翻译：在分布式共享存储器系统中使用高计数无效确认的方法和系统
公开(公告)号：US06718442B1
公开(公告)日：2004-04-06
申请号：US09910274
申请日：2001-07-20
申请人： William A. Huffman , Jeffrey S. Kuskin
发明人： William A. Huffman , Jeffrey S. Kuskin
IPC分类号： G06F1200
CPC分类号： G06F12/0826
摘要： A multiprocessor computer system includes a method and system of handling invalidation requests to a plurality of alias processors not sharing a line of memory in a computer system. A memory directory interface unit receives an invalidation request for a shared line of memory shared in a plurality of sharing processors. A superset of processors in the computer system that includes each of the sharing processors is determined that includes at least one alias processor not sharing the shared line of memory. An invalidation message is transmitted to each processor in the superset of processors. The number Na of alias processors in the superset of processors is determined and a superacknowledgement message is provided that is equivalent to acknowledging receipt of Na invalidation messages.
摘要翻译：多处理器计算机系统包括处理对在计算机系统中不共享存储器行的多个别名处理器的无效请求的方法和系统。存储器目录接口单元接收对在多个共享处理器中共享的共享存储线路的无效请求。确定包括每个共享处理器的计算机系统中的处理器的超集，其包括至少一个不共享共享存储器线的别名处理器。无效消息被传送到处理器的超集中的每个处理器。确定处理器超集中的别名处理器的数量Na，并且提供相当于确认接收到Na无效消息的超级确认消息。

5. 发明授权

US06938128B1 System and method for reducing memory latency during read requests 有权
标题翻译：用于在读请求期间减少内存延迟的系统和方法
公开(公告)号：US06938128B1
公开(公告)日：2005-08-30
申请号：US10725897
申请日：2003-12-02
申请人： Jeffrey S. Kuskin , William A. Huffman
发明人： Jeffrey S. Kuskin , William A. Huffman
IPC分类号： G08F12/00
CPC分类号： G06F12/0817
摘要： A processor (500) issues a read request for data. A processor interface (24) initiates a local search for the requested data and also forwards the read request to a memory directory (24) for processing. While the read request is processing, the processor interface (24) can determine if the data is available locally. If so, the data is transferred to the processor (500) for its use. The memory directory (24) processes the read request and generates a read response therefrom. The processor interface (24) receives the read response and determines whether the data was available locally. If so, the read response is discarded. If the data was not available locally, the processor interface (24) provides the read response to the processor (500).
摘要翻译：处理器（500）发出对数据的读取请求。处理器接口（24）发起对所请求的数据的本地搜索，并且还将读取的请求转发到存储器目录（24）以进行处理。当读取请求正在处理时，处理器接口（24）可以确定数据是否在本地可用。如果是这样，数据被传送到处理器（500）供其使用。存储器目录（24）处理读取请求并从其产生读取响应。处理器接口（24）接收读取响应并确定数据是否在本地可用。如果是这样，则读取响应被丢弃。如果数据在本地不可用，则处理器接口（24）向处理器（500）提供读取响应。

6. 发明授权

US06775742B2 Memory device storing data and directory information thereon, and method for providing the directory information and the data in the memory device 有权
标题翻译：在其上存储数据和目录信息的存储装置，以及用于在存储装置中提供目录信息和数据的方法
公开(公告)号：US06775742B2
公开(公告)日：2004-08-10
申请号：US09909693
申请日：2001-07-20
申请人： William A. Huffman , Jeffrey S. Kuskin
发明人： William A. Huffman , Jeffrey S. Kuskin
IPC分类号： G06F1200
CPC分类号： G06F12/0895
摘要： A memory device and method which provide at least one memory segment. The memory segment includes at least one first portion which is configured to store data. The memory segment also includes at least one second portion associated with the first portion, and which is configured to store directory information for at least one cache line thereon.
摘要翻译：提供至少一个存储器段的存储器件和方法。存储器段包括被配置为存储数据的至少一个第一部分。存储器段还包括与第一部分相关联的至少一个第二部分，并且被配置为存储其上的至少一个高速缓存行的目录信息。

7. 发明授权

US06915387B1 System and method for handling updates to memory in a distributed shared memory system 有权
标题翻译：用于处理分布式共享内存系统中内存更新的系统和方法
公开(公告)号：US06915387B1
公开(公告)日：2005-07-05
申请号：US09910589
申请日：2001-07-20
申请人： William A. Huffman , Jeffrey S. Kuskin
发明人： William A. Huffman , Jeffrey S. Kuskin
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0831
摘要： A processor (100) in a distributed shared memory computer system (10) receives ownership of data and initiates an initial update to memory request. A front side bus processor interface (24) forwards the initial update to memory request to a memory directory interface unit (22). The front side processor interface (24) may receive subsequent update to memory requests for the data from processors co-located on the same local bus. Front side bus processor interface (24) maintains a most recent subsequent update to memory in a queue (102). Once the data has been updated in its home memory (17), the memory directory interface unit (22) sends a writeback acknowledge to the front side bus processor interface (24). The most recent subsequent update to memory request in the queue (102) is then forwarded by the front side bus processor interface (24) to the memory directory interface unit (24) for processing.
摘要翻译：分布式共享存储器计算机系统（10）中的处理器（100）接收数据的所有权并启动对存储器请求的初始更新。前端总线处理器接口（24）将初始更新转发到存储器请求到存储器目录接口单元（22）。前侧处理器接口（24）可以接收来自同一位于同一局部总线上的来自处理器的数据的存储器请求的后续更新。前端总线处理器接口（24）维持对队列（102）中的存储器的最新的后续更新。一旦在其家庭存储器（17）中更新了数据，存储器目录接口单元（22）向前端总线处理器接口（24）发送回写确认。然后，队列（102）中对存储器请求的最新的后续更新然后由前端总线处理器接口（24）转发到存储器目录接口单元（24）以进行处理。

8. 发明授权

US06859863B1 Method and system for managing data at an input/output interface for a multiprocessor system 有权
标题翻译：用于在多处理器系统的输入/输出接口处管理数据的方法和系统
公开(公告)号：US06859863B1
公开(公告)日：2005-02-22
申请号：US09910631
申请日：2001-07-20
申请人： Steven C. Miller , Jeffrey S. Kuskin , William A. Huffman
发明人： Steven C. Miller , Jeffrey S. Kuskin , William A. Huffman
IPC分类号： G06F12/08 , G06F12/14 , G06F12/00
CPC分类号： G06F12/0817 , G06F12/1458 , G06F2212/621
摘要： A multiprocessor system and method includes a processing sub-system including a plurality of processors and a processor memory system. A network is operable to couple the processing sub-system to an input/output (I/O) sub-system. The I/O sub-system includes a plurality of I/O interfaces each operable to couple a peripheral device to the multiprocessor system. The I/O interfaces each include a local memory operable to store a copy of data from the processor memory system for use by a corresponding peripheral device and to delete the copy at a first time event. A directory for the processor is operable to identify the data as owned upon providing the copy to the I/O sub-system and to identify the data as unowned at a second time event.
摘要翻译：多处理器系统和方法包括包括多个处理器和处理器存储器系统的处理子系统。网络可操作以将处理子系统耦合到输入/输出（I / O）子系统。 I / O子系统包括多个I / O接口，每个I / O接口可操作以将外围设备耦合到多处理器系统。 I / O接口各自包括本地存储器，其可操作用于存储来自处理器存储器系统的数据副本，以供对应的外围设备使用，并在第一时间事件中删除副本。用于处理器的目录可操作以将数据提供给I / O子系统并将数据标识为在第二时间事件中未知的数据。

9. 发明授权

US06678798B1 System and method for reducing memory latency during read requests 有权
标题翻译：用于在读请求期间减少内存延迟的系统和方法
公开(公告)号：US06678798B1
公开(公告)日：2004-01-13
申请号：US09909701
申请日：2001-07-20
申请人： Jeffrey S. Kuskin , William A. Huffman
发明人： Jeffrey S. Kuskin , William A. Huffman
IPC分类号： G06F1200
CPC分类号： G06F12/0817 , G06F2212/1024
摘要： A processor (500) issues a read request for data. A processor interface (24) initiates a local search for the requested data and also forwards the read request to a memory directory (24) for processing. While the read request is processing, the processor interface (24) can determine if the data is available locally. If so, the data is transferred to the processor (500) for its use. The memory directory (24) processes the read request and generates a read response therefrom. The processor interface (24) receives the read response and determines whether the data was available locally. If so, the read response is discarded. If the data was not available locally, the processor interface (24) provides the read response to the processor (500).
摘要翻译：处理器（500）发出对数据的读取请求。处理器接口（24）发起对所请求的数据的本地搜索，并且还将读取的请求转发到存储器目录（24）以进行处理。当读取请求正在处理时，处理器接口（24）可以确定数据是否在本地可用。如果是这样，数据被传送到处理器（500）供其使用。存储器目录（24）处理读取请求并从其产生读取响应。处理器接口（24）接收读取响应并确定数据是否在本地可用。如果是这样，则读取响应被丢弃。如果数据在本地不可用，则处理器接口（24）向处理器（500）提供读取响应。

10. 发明授权

US06816947B1 System and method for memory arbitration 有权
标题翻译：内存仲裁的系统和方法
公开(公告)号：US06816947B1
公开(公告)日：2004-11-09
申请号：US09909705
申请日：2001-07-20
申请人： William A. Huffman
发明人： William A. Huffman
IPC分类号： G06F1200
CPC分类号： G06F13/1642 , G06F12/0813 , G06F2212/2542
摘要： A memory access arbitration scheme is provided where transactions to a Shared memory are stored in an arbitration queue. Prior to arbitration, the transactions are compared against the contents of cache memory, to determine which transactions will hit in cache, which will miss and which will be victims. Also prior to arbitration, the entries in the arbitration queue are grouped according to a transaction parameter, such as DRAM bank, Write to Bank, Read to Bank, etc. Arbitration is the performed among those groups which are ready for service. From the group winning arbitration, the oldest transaction is selected for servicing. Preferably, a collapsible queuing structure and method is used, such that once a transaction is serviced, higher order entries ripple down in the queue to make room for new entries while maintaining an oldest to newest relationship among the queue entries.
摘要翻译：提供存储器访问仲裁方案，其中向共享存储器的事务存储在仲裁队列中。在仲裁之前，将事务与高速缓存的内容进行比较，以确定哪些事务将在高速缓存中发生，哪些将丢失，哪些将成为受害者。另外在仲裁之前，仲裁队列中的条目根据事务参数进行分组，如DRAM银行，写入银行，读银行等。仲裁是在准备服务的组之间进行的。从获胜的仲裁中，选择最旧的交易进行维修。优选地，使用可折叠排队结构和方法，使得一旦事务被服务，高阶条目在队列中下降以便为新条目腾出空间，同时保持队列条目中最旧到最新的关系。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式