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1. 发明授权

US07468915B2 Method of reducing disturbs in non-volatile memory 有权
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US07468915B2
公开(公告)日：2008-12-23
申请号：US11538521
申请日：2006-10-04
申请人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C11/34
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

2. 发明授权

US06977844B2 Method of reducing disturbs in non-volatile memory 失效
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US06977844B2
公开(公告)日：2005-12-20
申请号：US11054084
申请日：2005-02-08
申请人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C16/02 , G11C16/12 , G11C16/04
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

3. 发明授权

US06888752B2 Method of reducing disturbs in non-volatile memory 有权
公开(公告)号：US06888752B2
公开(公告)日：2005-05-03
申请号：US10613098
申请日：2003-07-01
申请人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C16/02 , G11C16/12 , G11C16/04
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

4. 发明授权

US06717851B2 Method of reducing disturbs in non-volatile memory 有权
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US06717851B2
公开(公告)日：2004-04-06
申请号：US09759835
申请日：2001-01-10
申请人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C1604
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

5. 发明授权

US07145804B2 Method of reducing disturbs in non-volatile memory 有权
公开(公告)号：US07145804B2
公开(公告)日：2006-12-05
申请号：US11238911
申请日：2005-09-28
申请人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C11/34
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

6. 发明授权

US06570785B1 Method of reducing disturbs in non-volatile memory 有权
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US06570785B1
公开(公告)日：2003-05-27
申请号：US09703083
申请日：2000-10-31
申请人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang
发明人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang
IPC分类号： G11C1610
CPC分类号： G11C16/12
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage is adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

7. 发明申请

US20060023507A1 Method of reducing disturbs in non-volatile memory 有权
公开(公告)号：US20060023507A1
公开(公告)日：2006-02-02
申请号：US11238911
申请日：2005-09-28
申请人： John Mangan , Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
发明人： John Mangan , Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
IPC分类号： G11C7/10 , G11C11/34
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

8. 发明申请

US20070076510A1 Method of Reducing Disturbs in Non-Volatile Memory 有权
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US20070076510A1
公开(公告)日：2007-04-05
申请号：US11538521
申请日：2006-10-04
申请人： John Mangan , Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
发明人： John Mangan , Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
IPC分类号： G11C8/00
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

9. 发明申请

US20050146933A1 Method of reducing disturbs in non-volatile memory 失效
公开(公告)号：US20050146933A1
公开(公告)日：2005-07-07
申请号：US11054084
申请日：2005-02-08
申请人： Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
发明人： Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
IPC分类号： G11C16/02 , G11C16/12 , G11C16/04
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

10. 发明授权

US09186128B2 Needle biopsy device 有权
标题翻译：针活检装置
公开(公告)号：US09186128B2
公开(公告)日：2015-11-17
申请号：US12243367
申请日：2008-10-01
申请人： John Mugan , Brian Murphy , John McWeeney
发明人： John Mugan , Brian Murphy , John McWeeney
IPC分类号： A61B10/00 , A61B10/04 , A61B10/02 , A61B17/00 , A61B17/34 , A61B19/00
CPC分类号： A61B10/04 , A61B10/0233 , A61B10/0283 , A61B19/54 , A61B2010/045 , A61B2017/00424 , A61B2017/3413 , A61B2090/0801 , A61B2090/3925
摘要： A device for needle biopsy is provided. The device includes a handle member having proximal and distal portions. A proximal handle member is disposed to the proximal portion of the handle member and a distal handle member is disposed to the distal portion of the handle member. A sheath lumen is disposed within the handle member and extends from the distal portion of the handle member. A needle housing member is partially disposed to the proximal portion of the handle member and a needle is disposed within the sheath lumen. A plurality of protrusions are disposed upon the needle.
摘要翻译：提供一种用于针刺活检的装置。该装置包括具有近端部分和远端部分的手柄部件。近侧手柄构件设置在手柄构件的近侧部分，并且远端手柄构件设置在手柄构件的远端部分。护套管腔设置在手柄构件内并从手柄构件的远端部分延伸。针壳体构件部分地设置在手柄构件的近侧部分上，并且针被设置在鞘腔内。在针上设置有多个突起。

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