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1. 发明授权

US5351163A High Q monolithic MIM capacitor 失效
标题翻译：高Q单片MIM电容
公开(公告)号：US5351163A
公开(公告)日：1994-09-27
申请号：US998219
申请日：1992-12-30
申请人： Dale E. Dawson , Albert A. Burk, Jr. , Harlan C. Cramer , Ronald C. Brooks , Howell G. Henry
发明人： Dale E. Dawson , Albert A. Burk, Jr. , Harlan C. Cramer , Ronald C. Brooks , Howell G. Henry
IPC分类号： H01G4/08 , H01L21/02 , H01L29/92 , H01G4/10
CPC分类号： H01L28/40 , H01G4/08
摘要： A high Q monolithic metal-insulator-metal (MIM) capacitor utilizing a single crystal dielectric material. A dielectric membrane is epitaxially grown on a substrate. The membrane acts as an etch-stop when a backside etch is used to form a cavity in the substrate, resulting in a single crystal dielectric membrane spanning the cavity. Electrodes are formed on opposite surfaces of the membrane at the cavity location. For a shunt capacitor application, the bottom electrode is connected to the backside substrate metallization. For a series capacitor application, the bottom electrode is isolated from the backside metallization, but is connected to the topside circuitry through a via formed in the membrane. The membrane may consist of two dielectric layers, where the first layer is an etchstop material. In one embodiment the substrate and second dielectric layer are gallium arsenide and the first dielectric layer is aluminum gallium arsenide.
摘要翻译：使用单晶介质材料的高Q单片金属 - 绝缘体 - 金属（MIM）电容器。电介质膜在衬底上外延生长。当使用背面蚀刻在基板中形成空腔时，膜用作蚀刻停止，导致跨越空腔的单晶介质膜。在腔的位置处的膜的相对表面上形成电极。对于并联电容器应用，底部电极连接到背面基板金属化。对于串联电容器应用，底部电极与背面金属化隔离，但是通过形成在膜中的通孔连接到顶部电路。膜可以由两个介电层组成，其中第一层是蚀刻阻挡材料。在一个实施例中，衬底和第二电介质层是砷化镓，第一电介质层是砷化铝镓。

2. 发明授权

US08043965B2 Method of forming a through substrate via in a compound semiconductor 有权
标题翻译：在化合物半导体中形成贯通基板通孔的方法
公开(公告)号：US08043965B2
公开(公告)日：2011-10-25
申请号：US12369423
申请日：2009-02-11
申请人： Harlan C. Cramer , Dale E. Dawson
发明人： Harlan C. Cramer , Dale E. Dawson
IPC分类号： H01L21/44
CPC分类号： H01L21/76898
摘要： A method is provided for forming a through substrate via in a compound semiconductor having a transistor on a front side of the substrate. The method comprises forming a protective stop pad over a contact area on the front side of the substrate, forming a contact pad overlying the protective stop pad, such that the contact pad is in contact with a terminal of the transistor and plasma etching a backside of the substrate to form a contact coupling via to the protective stop pad. The method further comprises performing a chemical wet etch to remove the protective stop pad and depositing a conductive contact layer in the contact coupling via to provide a conductive contact to the contact pad.
摘要翻译：提供一种用于在具有在基板的正面上的晶体管的化合物半导体中形成贯穿基板通孔的方法。该方法包括在衬底的正面上的接触区域上形成保护停止焊盘，形成覆盖保护停止焊盘的接触焊盘，使得接触焊盘与晶体管的端子接触，等离子体蚀刻位于基板，以形成接触耦合通孔到保护止动垫。该方法还包括执行化学湿法蚀刻以去除保护性止动垫并在接触耦合通孔中沉积导电接触层，以向接触垫提供导电接触。

3. 发明申请

US20100203726A1 Method of Forming a Through Substrate Via in a Compound Semiconductor 有权
标题翻译：在复合半导体中形成通孔基板通孔的方法
公开(公告)号：US20100203726A1
公开(公告)日：2010-08-12
申请号：US12369423
申请日：2009-02-11
申请人： Harlan C. Cramer , Dale E. Dawson
发明人： Harlan C. Cramer , Dale E. Dawson
IPC分类号： H01L21/44
CPC分类号： H01L21/76898
摘要： A method is provided for forming a through substrate via in a compound semiconductor having a transistor on a front side of the substrate. The method comprises forming a protective stop pad over a contact area on the front side of the substrate, forming a contact pad overlying the protective stop pad, such that the contact pad is in contact with a terminal of the transistor and plasma etching a backside of the substrate to form a contact coupling via to the protective stop pad. The method further comprises performing a chemical wet etch to remove the protective stop pad and depositing a conductive contact layer in the contact coupling via to provide a conductive contact to the contact pad.
摘要翻译：提供一种用于在具有在基板的正面上的晶体管的化合物半导体中形成贯穿基板通孔的方法。该方法包括在衬底的正面上的接触区域上形成保护停止焊盘，形成覆盖保护停止焊盘的接触焊盘，使得接触焊盘与晶体管的端子接触，等离子体蚀刻位于基板，以形成接触耦合通孔到保护止动垫。该方法还包括执行化学湿法蚀刻以去除保护性止动垫并在接触耦合通孔中沉积导电接触层，以向接触垫提供导电接触。

4. 发明申请

US20140264273A1 SUPERLATTICE CRENELATED GATE FIELD EFFECT TRANSISTOR 有权
标题翻译：超级闸门场效应晶体管
公开(公告)号：US20140264273A1
公开(公告)日：2014-09-18
申请号：US13802747
申请日：2013-03-14
申请人： Robert S. Howell , Eric J. Stewart , Bettina A. Nechay , Justin A. Parke , Harlan C. Cramer , Jeffrey D. Hartman
发明人： Robert S. Howell , Eric J. Stewart , Bettina A. Nechay , Justin A. Parke , Harlan C. Cramer , Jeffrey D. Hartman
IPC分类号： H01L29/778 , H01L29/15
CPC分类号： H01L29/7784 , H01L29/0843 , H01L29/0847 , H01L29/1029 , H01L29/1037 , H01L29/155 , H01L29/2003 , H01L29/41766 , H01L29/66462
摘要： The present invention is directed to a device comprising an epitaxial structure comprising a superlattice structure having an uppermost 2DxG channel, a lowermost 2DxG channel and at least one intermediate 2DxG channel located between the uppermost and lowermost 2DxG channels, source and drain electrodes operatively connected to each of the 2DxG channels, and a plurality of trenches located between the source and drain electrodes. Each trench has length, width and depth dimensions defining a first sidewall, a second sidewall and a bottom located therebetween, the bottom of each trench being at or below the lowermost 2DxG channel. A crenelated gate electrode is located over the uppermost 2DxG channel, the gate electrode being located within each of the trenches such that the bottom surface of the gate electrode is in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of each of said trenches.
摘要翻译：本发明涉及一种包括外延结构的器件，该外延结构包括具有最上面的2DxG通道，最下面的2DxG通道和位于最上面和最下面的2DxG通道之间的至少一个中间2DxG通道的超晶格结构，源极和漏极之间可操作地连接到每个的2DxG通道，以及位于源极和漏极之间的多个沟槽。每个沟槽具有限定第一侧壁，第二侧壁和位于其间的底部的长度，宽度和深度尺寸，每个沟槽的底部位于或最下面的2DxG通道。栅极电极位于最上面的2DxG通道之上，栅电极位于每个沟槽内，使得栅电极的底表面与每个的第一侧壁表面，底表面和第二侧壁表面并置的壕沟。

5. 发明授权

US09202906B2 Superlattice crenelated gate field effect transistor 有权
标题翻译：超晶格栅极场效应晶体管
公开(公告)号：US09202906B2
公开(公告)日：2015-12-01
申请号：US13802747
申请日：2013-03-14
申请人： Robert S. Howell , Eric J. Stewart , Bettina A. Nechay , Justin A. Parke , Harlan C. Cramer , Jeffrey D. Hartman
发明人： Robert S. Howell , Eric J. Stewart , Bettina A. Nechay , Justin A. Parke , Harlan C. Cramer , Jeffrey D. Hartman
IPC分类号： H01L29/06 , H01L29/778 , H01L29/417 , H01L29/66 , H01L29/10 , H01L29/15 , H01L29/20
CPC分类号： H01L29/7784 , H01L29/0843 , H01L29/0847 , H01L29/1029 , H01L29/1037 , H01L29/155 , H01L29/2003 , H01L29/41766 , H01L29/66462
摘要： The present invention is directed to a device comprising an epitaxial structure comprising a superlattice structure having an uppermost 2DxG channel, a lowermost 2DxG channel and at least one intermediate 2DxG channel located between the uppermost and lowermost 2DxG channels, source and drain electrodes operatively connected to each of the 2DxG channels, and a plurality of trenches located between the source and drain electrodes. Each trench has length, width and depth dimensions defining a first sidewall, a second sidewall and a bottom located therebetween, the bottom of each trench being at or below the lowermost 2DxG channel. A crenelated gate electrode is located over the uppermost 2DxG channel, the gate electrode being located within each of the trenches such that the bottom surface of the gate electrode is in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of each of said trenches.
摘要翻译：本发明涉及一种包括外延结构的器件，该外延结构包括具有最上面的2DxG通道，最下面的2DxG通道和位于最上面和最下面的2DxG通道之间的至少一个中间2DxG通道的超晶格结构，源极和漏极之间可操作地连接到每个的2DxG通道，以及位于源电极和漏电极之间的多个沟槽。每个沟槽具有限定第一侧壁，第二侧壁和位于其间的底部的长度，宽度和深度尺寸，每个沟槽的底部位于或最下面的2DxG通道。栅极电极位于最上面的2DxG通道之上，栅电极位于每个沟槽内，使得栅电极的底表面与每个的第一侧壁表面，底表面和第二侧壁表面并置的壕沟。

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