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1. 发明授权

US08059445B2 Ferroelectric memory 有权
标题翻译：铁电存储器
公开(公告)号：US08059445B2
公开(公告)日：2011-11-15
申请号：US12563950
申请日：2009-09-21
申请人： Daisuke Hashimoto , Daisaburo Takashima , Hidehiro Shiga
发明人： Daisuke Hashimoto , Daisaburo Takashima , Hidehiro Shiga
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/406
摘要： A ferroelectric memory according to an embodiment of the present invention includes a memory cell array including plural memory cells, and provided with plural word lines, plural bit lines, and plural plate lines, each of the plate lines corresponding to at least two of the word lines, an access control circuit configured to perform an access operation to a selected cell which is selected from the memory cells, and a refresh control circuit configured to perform a refresh operation, in a background of the access operation, on a refresh cell which is selected from the memory cells, the refresh control circuit performing the refresh operation when a plate line connected to the selected cell and a bit line connected to the selected cell are at the same potential after the access operation.
摘要翻译：根据本发明的实施例的铁电存储器包括：存储单元阵列，包括多个存储单元，并且具有多个字线，多个位线和多个板线，每个板线对应于该字中的至少两个线路，被配置为对从所述存储器单元中选择的所选择的单元执行访问操作的访问控制电路;以及刷新控制电路，被配置为在所述访问操作的后台中执行刷新操作，所述更新单元是从所述存储单元中选择所述刷新控制电路，所述刷新控制电路在连接到所选择的单元的板线和连接到所选择的单元的位线之间执行刷新操作，在所述访问操作之后处于相同的电位。

2. 发明授权

US07965536B2 Ferroelectric memory device 有权
标题翻译：铁电存储器件
公开(公告)号：US07965536B2
公开(公告)日：2011-06-21
申请号：US12560206
申请日：2009-09-15
申请人： Daisuke Hashimoto , Daisaburo Takashima , Hidehiro Shiga
发明人： Daisuke Hashimoto , Daisaburo Takashima , Hidehiro Shiga
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： According to an aspect of the present invention, there is provided a ferroelectric memory device including: a cell unit including: a first select transistor having a first source, a first drain, and a first gate, one of the first source and the first drain being connected to a bit line; and a memory cell unit having a plurality of first memory cells, each of the first memory cells including a first ferroelectric capacitor and a first memory transistor; and a ferroelectric memory fuse including: a second select transistor having a second source, a second drain, and a second gate connected to a second select line, one of the second source and the second drain being connected to one end of the bit line; and a memory fuse unit having a plurality of second memory cells, each of the second memory cells including a second ferroelectric capacitor and a second memory transistor.
摘要翻译：根据本发明的一个方面，提供了一种铁电存储器件，它包括：一个单元单元，包括：具有第一源极，第一漏极和第一栅极的第一选择晶体管，第一源极和第一漏极之一连接到位线; 以及具有多个第一存储单元的存储单元单元，每个第一存储单元包括第一铁电电容器和第一存储晶体管; 以及铁电存储器熔丝，包括：第二选择晶体管，具有连接到第二选择线的第二源极，第二漏极和第二栅极，所述第二源极和所述第二漏极中的一个连接到所述位线的一端; 以及具有多个第二存储单元的存储器熔丝单元，每个第二存储单元包括第二铁电电容器和第二存储晶体管。

3. 发明授权

US08238137B2 Ferroelectric random access memory device 有权
标题翻译：铁电随机存取存储器件
公开(公告)号：US08238137B2
公开(公告)日：2012-08-07
申请号：US12562051
申请日：2009-09-17
申请人： Daisuke Hashimoto , Daisaburo Takashima
发明人： Daisuke Hashimoto , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric random access memory device has a first bit line, a first ferroelectric capacitor, a second bit line, a second ferroelectric capacitor and a first to fourth MOS transistor. The first bit line is changed to a first data potential according to first data stored in the first ferroelectric capacitor, the second bit line is changed to a second data potential according to second data obtained by inverting a logic of the first data, and then the second MOS transistor and the fourth MOS transistor are turned on.
摘要翻译：铁电随机存取存储器件具有第一位线，第一铁电电容器，第二位线，第二铁电电容器和第一至第四MOS晶体管。根据存储在第一铁电电容器中的第一数据将第一位线改变为第一数据电位，根据通过反转第一数据的逻辑获得的第二数据将第二位线改变为第二数据电位，然后第二MOS晶体管和第四MOS晶体管导通。

4. 发明授权

US08199554B2 Ferro-electric random access memory apparatus 失效
标题翻译：铁电随机存取存储器
公开(公告)号：US08199554B2
公开(公告)日：2012-06-12
申请号：US12876984
申请日：2010-09-07
申请人： Daisuke Hashimoto , Daisaburo Takashima
发明人： Daisuke Hashimoto , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferro-electric random access memory apparatus has a memory cell array in which a plurality of memory cells each formed of a ferro-electric capacitor and a transistor are arranged, word lines are disposed to select a memory cell, plate lines are disposed to apply a voltage to a first end of the ferro-electric capacitor in a memory cell, and bit lines are disposed to read cell data from a second end of the ferro-electric capacitor in the memory cell. The ferro-electric random access memory apparatus has a sense amplifier which senses and amplifies a signal read from the ferro-electric capacitor onto the bit line. The ferro-electric random access memory apparatus has a bit line potential control circuit which exercises control to pull down a voltage on an adjacent bit line adjacent to the selected bit line onto which the signal is read, before operation of the sense amplifier at time of data readout.
摘要翻译：铁电随机存取存储装置具有其中布置有由铁电电容器和晶体管形成的多个存储单元的存储单元阵列，设置字线以选择存储单元，设置板线以应用存储单元中的铁电电容器的第一端的电压和位线被设置为从存储单元中的铁电电容器的第二端读取单元数据。铁电随机存取存储装置具有感测放大器，其感测并放大从铁电电容器读取到位线上的信号。铁电随机存取存储装置具有位线电位控制电路，该位线电位控制电路在该读出放大器的操作之前进行控制以在与读取信号的所选位线相邻的相邻位线上下拉电压数据读出。

5. 发明授权

US08174913B2 Semiconductor memory device and driving method of the same 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US08174913B2
公开(公告)日：2012-05-08
申请号：US12703548
申请日：2010-02-10
申请人： Daisuke Hashimoto , Daisaburo Takashima
发明人： Daisuke Hashimoto , Daisaburo Takashima
IPC分类号： G11C7/00 , G11C17/18 , G11C11/22 , G11C11/34 , G11C8/00
CPC分类号： G11C29/24 , G11C11/22 , G11C17/143 , G11C29/785
摘要： A memory includes a cell region; a spare region including a spare block; a fuse region storing remedy information necessary for an access to the spare block instead of a remedy target block, the fuse region comprising non-defective cells in the remedy target block, or including cells in a first block of the spare region; an initial reading fuse storing a block address for identifying the remedy target block or the first block allocated as the fuse region, and a selection address for selecting a region in the remedy target block or a region in the first block allocated as the fuse region; and a controller configured to acquire the remedy information from the fuse region based on the block address and the selection address, and to change the access to the remedy target block to the access to the spare block based on the remedy information.
摘要翻译：存储器包括单元区域; 包括备用区的备用区; 熔丝区域，其存储访问所述备用块而不是补救目标块所需的补救信息，所述熔丝区域包括所述补救目标块中的无缺陷单元，或者包括所述备用区域的第一块中的单元; 存储用于识别补救目标块的块地址的初始读取熔丝或分配为熔丝区的第一块的初始读取熔丝，以及用于选择补救目标块中的区域或分配为熔丝区域的第一块中的区域的选择地址; 以及控制器，被配置为基于所述块地址和所述选择地址从所述保险丝区域获取补救信息，并且基于所述补救信息来将对所述补救目标块的访问改变为对所述备用块的访问。

6. 发明申请

US20100110755A1 FERROELECTRIC RANDOM ACCESS MEMORY DEVICE 有权
标题翻译：电磁随机访问存储器件
公开(公告)号：US20100110755A1
公开(公告)日：2010-05-06
申请号：US12562051
申请日：2009-09-17
申请人： Daisuke Hashimoto , Daisaburo Takashima
发明人： Daisuke Hashimoto , Daisaburo Takashima
IPC分类号： G11C11/22 , G11C11/24 , G11C7/00
CPC分类号： G11C11/22
摘要： A ferroelectric random access memory device has a first bit line, a first ferroelectric capacitor, a second bit line, a second ferroelectric capacitor and a first to fourth MOS transistor. The first bit line is changed to a first data potential according to first data stored in the first ferroelectric capacitor, the second bit line is changed to a second data potential according to second data obtained by inverting a logic of the first data, and then the second MOS transistor and the fourth MOS transistor are turned on.
摘要翻译：铁电随机存取存储器件具有第一位线，第一铁电电容器，第二位线，第二铁电电容器和第一至第四MOS晶体管。根据存储在第一铁电电容器中的第一数据将第一位线改变为第一数据电位，根据通过反转第一数据的逻辑获得的第二数据将第二位线改变为第二数据电位，然后第二MOS晶体管和第四MOS晶体管导通。

7. 发明授权

US09026764B2 Memory system performing wear leveling based on deletion request 有权
标题翻译：基于删除请求执行磨损均衡的内存系统
公开(公告)号：US09026764B2
公开(公告)日：2015-05-05
申请号：US13420808
申请日：2012-03-15
申请人： Daisuke Hashimoto
发明人： Daisuke Hashimoto
IPC分类号： G06F12/00 , G06F12/02 , G06F12/10 , G06F13/00
CPC分类号： G06F12/0246 , G06F12/023 , G06F12/10 , G06F2212/7201 , G06F2212/7205 , G06F2212/7211
摘要： A memory system of a embodiments includes a first storing area having physical blocks and a second storing area recording a logical to physical translation table and an erasure count table keeping data erasure count in physical blocks. The memory system of the embodiments includes a controller which, when a logical address for deletion is notified, obtains data erasure count of a deletion physical block including a deletion area specified by the physical address corresponding to the logical address, and when a physical block having a small erasure count not more than a predetermined rate of the data erasure count exists in the erasure count table, reads out valid data for the memory system in the physical block having a small erasure count onto the second storing area, writes the above data into the deletion area, and invalidates the valid data in the physical block having a small erasure count.
摘要翻译：实施例的存储器系统包括具有物理块的第一存储区域和记录逻辑到物理转换表的第二存储区域和在物理块中保持数据擦除计数的擦除计数表。实施例的存储器系统包括控制器，当通知用于删除的逻辑地址时，获得包括由对应于逻辑地址的物理地址指定的删除区域的删除物理块的数据擦除计数，以及当具有在擦除计数表中存在不大于数据擦除计数的预定速率的小擦除次数，将具有小擦除次数的物理块中的存储器系统的有效数据读出到第二存储区域，将上述数据写入删除区域，使具有小擦除次数的物理块中的有效数据无效。

8. 发明申请

US20140147748A1 NEGATIVE ELECTRODE MATERIAL FOR LITHIUM SECONDARY BATTERY 审中-公开
标题翻译：用于锂二次电池的负极电极材料
公开(公告)号：US20140147748A1
公开(公告)日：2014-05-29
申请号：US13877976
申请日：2011-10-11
申请人： Koji Hisayuki , Daisuke Hashimoto
发明人： Koji Hisayuki , Daisuke Hashimoto
IPC分类号： H01M4/36
CPC分类号： H01M4/366 , C22C1/08 , H01M4/134 , H01M4/38 , H01M4/46 , H01M4/463 , H01M4/661 , H01M4/80 , H01M10/052 , H01M10/0585 , H01M2004/021
摘要： A lithium secondary battery negative electrode material 1 is in the form of a foil 2 or a plate, and includes a core layer 3 having electrical conductivity, and a porous layer 4 which is formed on at least one surface of the core layer 3, and which contains Al in an amount of 90 mass % or more. The porous layer 4 has a porosity of 30 to 70 vol. %. Pores 5 formed in the porous layer 4 have a pore size of 0.1 to 15 μm. The lithium secondary battery negative electrode material 1 realizes prolongation of the cycle life of a lithium secondary battery.
摘要翻译：锂二次电池负极材料1为箔2或板的形式，并且包括具有导电性的芯层3和形成在芯层3的至少一个表面上的多孔层4，以及其含有量为90质量％以上的Al。多孔层4的孔隙率为30〜70体积％。％。在多孔层4中形成的孔5的孔径为0.1〜15μm。锂二次电池负极材料1实现了锂二次电池的循环寿命的延长。

9. 发明申请

US20140113189A1 NEGATIVE ELECTRODE ACTIVE SUBSTANCE FOR LITHIUM SECONDARY BATTERY AND METHOD FOR PRODUCING SAME 有权
标题翻译：用于锂二次电池的负极电极活性物质及其生产方法
公开(公告)号：US20140113189A1
公开(公告)日：2014-04-24
申请号：US14110507
申请日：2011-10-11
申请人： Daisuke Hashimoto , Koji Hisayuki
发明人： Daisuke Hashimoto , Koji Hisayuki
IPC分类号： H01M4/46 , B02C23/06 , H01M4/36
CPC分类号： H01M4/463 , B02C23/06 , H01M4/134 , H01M4/1395 , H01M4/36 , H01M4/38 , H01M4/621 , H01M4/624 , H01M10/052 , Y02E60/122 , Y02P70/54
摘要： The present invention provides an anode material for a lithium secondary battery, which material realizes prolongation of the cycle life of a lithium secondary battery. The present invention relates to an anode active material for a lithium secondary battery, the active material containing a powder produced by a step of forming an etched foil through etching of both surfaces of a foil of Al having a purity of 90 mass % or higher, and a step of shredding the etched foil, the steps being carried out in this order.
摘要翻译：本发明提供了一种用于锂二次电池的负极材料，该材料实现了锂二次电池的循环寿命的延长。本发明涉及一种锂二次电池用负极活性物质，该活性物质含有通过蚀刻具有纯度为90质量％以上的Al的箔的两面来形成蚀刻箔的工序而制造的粉末，以及切割蚀刻的箔的步骤，该步骤以该顺序进行。

10. 发明申请

US20140000927A1 BUS-BAR SET AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：总线设置及其制造方法
公开(公告)号：US20140000927A1
公开(公告)日：2014-01-02
申请号：US13982614
申请日：2012-02-28
申请人： Daisuke Hashimoto , Kouji Fukumoto , Masaharu Suetani
发明人： Daisuke Hashimoto , Kouji Fukumoto , Masaharu Suetani
IPC分类号： H01B7/00 , H01B13/06
CPC分类号： H01B7/0018 , H01B13/06 , H01R11/288 , H01R43/24 , H02G5/005 , Y10T29/4922
摘要： The present invention is intended to provide a bus bar set that has excellent heat dissipation performance and mounting workability and prevents excessive heat generation due to an electrical connection failure, even when a cross section area of a conductive body is large. A bus bar set has a plurality of multilayer bus bars and an insulating member. The multilayer bus bars each include an intermediate portion having a plurality of layered plate-shaped conductive bodies and terminal portions having conductive bodies extending from two ends of the intermediate portion and connected to other members. The insulating member is composed of a flexible insulating body having a flat external shape, and covers and integrally connects the intermediate portions of the plurality of multilayer bus bars aligned in parallel with gaps therebetween on one plane.
摘要翻译：本发明旨在提供一种具有优异的散热性能和安装加工性的母线组，并且即使当导电体的横截面积大时也能防止由于电连接故障而导致的过热发生。母线组具有多个多层母线和绝缘构件。多层母线棒各自包括具有多个层叠的板状导电体的中间部分和具有从中间部分的两端延伸并连接到其它部件的导电体的端子部分。绝缘构件由具有平坦外形的柔性绝缘体构成，并且在一个平面上覆盖并整体地连接多个多层汇流条的中间部分与其间的间隙平行排列。

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