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1. 发明申请

US20090138748A1 APPARATUS AND METHOD FOR MICRO PERFORMANCE TUNING OF A CLOCKED DIGITAL SYSTEM 失效
标题翻译：一种时钟数字系统的微观性能调谐的装置和方法
公开(公告)号：US20090138748A1
公开(公告)日：2009-05-28
申请号：US11946466
申请日：2007-11-28
申请人： Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： An apparatus and method for micro-tuning an effective clock frequency of a core in a microprocessor. The apparatus includes a microprocessor having at least one core with logic configured to transition between states, a clock signal coupled to the microprocessor, the clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period. The apparatus further including at least one voltage drop sensor coupled to the core, the sensor being configured to generate an output signal for detecting a voltage drop in the core and to determine whether or not the output signal is detected within the clock period and, if the output signal is not detected, the sensor dynamically adjusts the clock period of the clock signal provided to the core to allow more time to complete state transitions, such that, dynamically adjusting the clock period effectively changes an effective core clock frequency.
摘要翻译：一种用于微调微处理器中的核心的有效时钟频率的装置和方法。该装置包括具有至少一个具有逻辑的核心的微处理器，其配置成在状态之间转换，耦合到微处理器的时钟信号，时钟信号具有基于最坏情况时钟频率和预定时钟周期的预定时钟频率。所述装置还包括耦合到所述芯的至少一个电压降传感器，所述传感器被配置为产生用于检测所述磁芯中的电压降的输出信号，并且确定在所述时钟周期内是否检测到所述输出信号，以及如果输出信号未检测到，传感器动态地调整提供给核心的时钟信号的时钟周期，以允许更多的时间完成状态转换，使得动态调整时钟周期有效地改变有效的核心时钟频率。

2. 发明申请

US20090138737A1 APPARATUS, METHOD AND PROGRAM PRODUCT FOR ADAPTIVE REAL-TIME POWER AND PERFOMANCE OPTIMIZATION OF MULTI-CORE PROCESSORS 有权
标题翻译：用于自适应实时功率和多核处理器的性能优化的装置，方法和程序产品
公开(公告)号：US20090138737A1
公开(公告)日：2009-05-28
申请号：US11946522
申请日：2007-11-28
申请人： Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/32
摘要： An apparatus, method and program product for optimizing core performance and power in of a multi-core processor. The apparatus includes a multi-core processor coupled to a clock source providing a clock frequency to one or more cores, an independent power supply coupled to each core for providing a supply voltage to each core and a Phase-Locked Loop (PLL) circuit coupled to each core for dynamically adjusting the clock frequency provided to each core. The apparatus further includes a controller coupled to each core and being configured to collect performance data and power consumption data measured for each core and to adjust, using the PLL circuit, a supply voltage provided to a core, such that, the operational core frequency of the core is greater than a specification core frequency preset for the core and, such that, core performance and power consumption is optimized.
摘要翻译：一种用于优化多核处理器的核心性能和功耗的设备，方法和程序产品。该装置包括耦合到时钟源的多核处理器，其为一个或多个核心提供时钟频率，耦合到每个核心的独立电源，用于向每个核心提供电源电压，以及耦合到锁相环到每个核心，用于动态调整提供给每个核心的时钟频率。该装置还包括耦合到每个核心并被配置为收集针对每个核心测量的性能数据和功耗数据的控制器，并且使用PLL电路来调整提供给核心的电源电压，使得所述操作核心频率核心大于为核心预设的规格核心频率，从而优化核心性能和功耗。

3. 发明申请

US20090134844A1 APPARATUS AND METHOD FOR RECYCLING AND REUSING CHARGE IN AN ELECTRONIC CIRCUIT 有权
标题翻译：用于在电子电路中回收和重新充电的装置和方法
公开(公告)号：US20090134844A1
公开(公告)日：2009-05-28
申请号：US11946550
申请日：2007-11-28
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： H02J7/00
CPC分类号： H02J7/345
摘要： An apparatus and method for recycling and reusing charge in an electronic circuit. The apparatus includes at least one capacitor coupled to a circuit block in the electronic circuit, the capacitor being configured to collect current charge consumed by the circuit block when set to a charge collection mode, and a voltage level comparator configured to detect a fully charged state when the capacitor is fully charged. Further, the apparatus includes a first electrical switch configured to allow, once the fully charged state is detected, the capacitor to switch to a discharge mode for discharging the current charge collected back into the power supply for reuse by the electrical system and a second switch configured to allow, after the capacitor has fully discharged the current charge collected, the capacitor to switch back to the charge collection mode, such that, the current charge is recycled and reused by the electrical system.
摘要翻译：一种用于在电子电路中再循环和再利用电荷的装置和方法。该装置包括耦合到电子电路中的电路块的至少一个电容器，电容器被配置为当设置为电荷收集模式时收集由电路块消耗的当前电荷;以及电压电平比较器，被配置为检测完全充电状态当电容器充满电时。此外，该装置包括第一电开关，其被配置为允许一旦检测到完全充电状态，电容器切换到放电模式，用于将收集的当前电荷放回电源供电系统和第二开关配置为允许在电容器已经完全放电所收集的当前电荷之后，电容器切换回电荷收集模式，使得当前电荷被电气系统再循环和再利用。

4. 发明授权

US08138563B2 Circuit structures and methods with BEOL layers configured to block electromagnetic edge interference 有权
标题翻译： BEOL层的电路结构和方法被配置为阻止电磁边缘干扰
公开(公告)号：US08138563B2
公开(公告)日：2012-03-20
申请号：US12188243
申请日：2008-08-08
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic
IPC分类号： H01L29/82
CPC分类号： H01L23/5225 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.
摘要翻译：提供了后端行（BEOL）电路结构和方法来阻止外部来源或内部产生的电磁边缘干扰。一个这样的BEOL电路结构包括支撑一个或多个集成电路的半导体衬底和设置在半导体衬底上的多个BEOL层。多个BEOL层延伸到电路结构的边缘并且包括邻近电路结构的边缘布置的至少一个垂直延伸的导电图案。至少部分地由设置在多个BEOL层中的多个元件限定垂直延伸的导电图案。多个元件在电路结构的边缘沿其第一方向或第二方向均匀地排列在其至少一部分上。多个元件的大小和尺寸设置在第一方向或第二方向上，以阻止特定波长的电磁干扰通过。

5. 发明授权

US08273648B2 Circuit structures and methods with BEOL layers configured to block electromagnetic edge interference 有权
公开(公告)号：US08273648B2
公开(公告)日：2012-09-25
申请号：US13369592
申请日：2012-02-09
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic
IPC分类号： H01L21/3205
CPC分类号： H01L23/5225 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.

6. 发明申请

US20080177506A1 METHOD AND SYSTEM FOR TESTING PROCESSOR CORES 有权
标题翻译：用于测试加工器的方法和系统
公开(公告)号：US20080177506A1
公开(公告)日：2008-07-24
申请号：US11624329
申请日：2007-01-18
申请人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G06F15/00
CPC分类号： G06F11/24 , G01R31/3004 , G01R31/31721 , G01R31/318505
摘要： Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于测试多核处理器芯片结构。单个处理器核心电源电压通过控制每个核心的单独电源来提供，在一个方面，以确保一个或多个核心以按照一个或多个性能规格的时钟速率运行。在一个示例中，提供给第一处理核心的第一电源电压与提供给第二处理核心的第二核心电源电压不同，两个核心都遵循参考时钟速率规范操作。核心电源电压可以从通过逐渐提高或降低第一电源电压而导出的有序离散电源电压中选择，任选地，其中所选择的电源电压还使得核能够在另一性能规格内操作。

7. 发明申请

US20080262777A1 SYSTEM FOR TESTING PROCESSOR CORES 有权
标题翻译：测试加工器系统
公开(公告)号：US20080262777A1
公开(公告)日：2008-10-23
申请号：US12128075
申请日：2008-05-28
申请人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G01R31/00 , G06F15/00
CPC分类号： G06F11/24 , G01R31/3004 , G01R31/31721 , G01R31/318505
摘要： Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于测试多核处理器芯片结构。单个处理器核心电源电压通过控制每个核心的单独电源来提供，在一个方面，以确保一个或多个核心以按照一个或多个性能规格的时钟速率运行。在一个示例中，提供给第一处理核心的第一电源电压与提供给第二处理核心的第二核心电源电压不同，两个核心都遵循参考时钟速率规范操作。核心电源电压可以从通过逐渐提高或降低第一电源电压而导出的有序离散电源电压中选择，任选地，其中所选择的电源电压还使得核能够在另一性能规格内操作。

8. 发明申请

US20080178023A1 METHOD AND SYSTEM FOR INDEPENDENT PROCESSOR VOLTAGE SUPPLY 有权
标题翻译：独立处理器电压供应方法与系统
公开(公告)号：US20080178023A1
公开(公告)日：2008-07-24
申请号：US11624333
申请日：2007-01-18
申请人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： Systems, methods and program codes are provided for selectively adjusting multi-core processor chip structure individual processor core power supply voltages through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. Nominal power supply voltage is supplied to a first processing core, and a second core power supply voltage greater or lower than the nominal power supply voltage is supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. The second power supply voltage may be selected from ordered discrete supply voltages derived by progressively lowering the nominal supply voltage, optionally wherein the selected supply voltage also enables the second core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于通过控制每个核心的单个电源来选择性地调整多核处理器核心电源电压的多核处理器芯片结构，以确保一个或多个内核按照一个时钟速率运行或更多性能规格。标称电源电压被提供给第一处理核心，并且大于或低于标称电源电压的第二核心电源电压被提供给第二处理核心，两个核心都遵守参考时钟速率规范。第二电源电压可以从通过逐渐降低标称电源电压而导出的有序的离散电源电压中选择，可选地，其中所选择的电源电压还使得第二磁芯能够在另一性能规范内操作。

9. 发明申请

US20090150555A1 MEMORY TO MEMORY COMMUNICATION AND STORAGE FOR HYBRID SYSTEMS 有权
标题翻译：对混合系统的记忆体通信和存储的记忆
公开(公告)号：US20090150555A1
公开(公告)日：2009-06-11
申请号：US11951709
申请日：2007-12-06
申请人： Moon J. Kim , Rajaram B. krishnamurthy , James R. Moulic
发明人： Moon J. Kim , Rajaram B. krishnamurthy , James R. Moulic
IPC分类号： G06F15/16
CPC分类号： H04L67/1097 , G06F3/0605 , G06F3/0638 , G06F3/064 , G06F3/067
摘要： The present invention relates to memory to memory communication and storage for hybrid systems. Under the present invention, a data stream is received on a first computing device of a hybrid system. An attempt is made to store the data stream on the first computing device up to a per stream limit and a total storage limit of the first computing device. It is then determined whether to store at least a portion of the data stream on a second computing device of the hybrid system that is in communication with the first computing device. This decision is based on the per stream limit and the total storage limit of the first computing device as well as a per stream limit and a total storage limit of the second computing device. Thereafter, the at least a portion of the data stream and a control signal are communicated to the second computing device for storage.
摘要翻译：本发明涉及用于混合系统的存储器到存储器通信和存储。在本发明中，在混合系统的第一计算设备上接收数据流。尝试将数据流存储在第一计算设备上，直到第一计算设备的每流限制和总存储限制。然后确定是否将数据流的至少一部分存储在与第一计算设备通信的混合系统的第二计算设备上。该决定基于第一计算设备的每流限制和总存储限制以及第二计算设备的每流限制和总存储限制。此后，数据流的至少一部分和控制信号被传送到第二计算设备以进行存储。

10. 发明申请

US20080181471A1 UNIVERSAL IMAGE PROCESSING 有权
标题翻译：通用图像处理
公开(公告)号：US20080181471A1
公开(公告)日：2008-07-31
申请号：US11668875
申请日：2007-01-30
申请人： William Hyun-Kee Chung , Bruce A. Foster , Moon J. Kim , James R. Moulic
发明人： William Hyun-Kee Chung , Bruce A. Foster , Moon J. Kim , James R. Moulic
IPC分类号： G06K9/00
CPC分类号： G06T1/00 , A61B6/463 , A61B6/464 , A61B6/5247 , A61B6/563 , G06F19/00 , G06F19/321 , G06T7/00 , G06T11/003
摘要： The present invention provides a universal and centralized image (e.g., medical, bio-molecular, etc.) processing system platform. The invention permits sharing both computation and visualization across a single universal platform, thus allowing for sharing of computing resources and visualization of images on a variety of imaging (client) devices without high-performance graphical display cards. In a typical embodiment a (e.g., medical) image 2D linear registration algorithm is implemented on a Cell Broadband Engine processor, which has nine processor cores on a chip and has a 4-way SIMD unit for each core.
摘要翻译：本发明提供了一种通用且集中的图像（例如医疗，生物分子等）处理系统平台。本发明允许在单个通用平台上共享计算和可视化，从而允许在不具有高性能图形显示卡的各种成像（客户端）设备上共享计算资源和可视化图像。在典型的实施例中，在Cell Broadband Engine处理器上实现（例如，医学）图像2D线性注册算法，该处理器在芯片上具有九个处理器核心，并且具有用于每个核心的4路SIMD单元。

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