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1. 发明授权

US08946869B2 Integrated circuit for detecting defects of through chip via 有权
标题翻译：用于检测芯片通孔缺陷的集成电路
公开(公告)号：US08946869B2
公开(公告)日：2015-02-03
申请号：US13041003
申请日：2011-03-04
申请人： Dae-Suk Kim , Jong-Chern Lee , Chul Kim
发明人： Dae-Suk Kim , Jong-Chern Lee , Chul Kim
IPC分类号： H01L29/00 , H01L29/80 , H01L23/48 , H01L21/66 , G01R31/28 , H01L23/00
CPC分类号： H01L22/34 , G01R31/2853 , G01R31/2884 , H01L23/481 , H01L24/05 , H01L2225/06544 , H01L2225/06596 , H01L2924/12032 , H01L2924/13091 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.
摘要翻译：在晶圆级别检测贯通硅通孔是否具有缺陷的集成电路。集成电路包括：半导体衬底;通孔构造成形成在半导体衬底中以从半导体衬底的表面延伸到一定深度的通硅通孔，输出焊盘和电流通路提供单元，其被配置为提供电流，在测试模式期间，在半导体衬底和贯穿硅通孔之间流动到输出焊盘。

2. 发明授权

US08107310B2 Semiconductor memory device and method for operating the same 失效
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08107310B2
公开(公告)日：2012-01-31
申请号：US12650594
申请日：2009-12-31
申请人： Dae-Suk Kim , Jong-Chern Lee
发明人： Dae-Suk Kim , Jong-Chern Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40611 , G11C11/40618
摘要： A semiconductor memory device includes a bank having a plurality of mats, an address counting unit configured to receive an auto-refresh command consecutively applied at predetermined intervals corresponding to a number of the mats, and sequentially count an internal address in response to the auto-refresh command, and an address transferring unit configured to enable the plurality of mats in response to the auto-refresh command, and transfer the internal address to the plurality of mats at predetermined time intervals.
摘要翻译：半导体存储器件包括具有多个垫的存储体，地址计数单元，被配置为接收以对应于所述垫的数量的预定间隔连续地施加的自动刷新命令，并且响应于所述自动刷新命令顺序计数内部地址，刷新命令和地址传送单元，被配置为响应于所述自动刷新命令启用所述多个垫，并且以预定的时间间隔将所述内部地址传送到所述多个垫。

3. 发明授权

US07622962B2 Sense amplifier control signal generating circuit of semiconductor memory apparatus 失效
标题翻译：半导体存储装置的感应放大器控制信号发生电路
公开(公告)号：US07622962B2
公开(公告)日：2009-11-24
申请号：US11826924
申请日：2007-07-19
申请人： Dae-Suk Kim , Jong Chern Lee
发明人： Dae-Suk Kim , Jong Chern Lee
IPC分类号： G01R19/00
CPC分类号： G11C7/08
摘要： A sense amplifier control signal generating circuit of a semiconductor memory apparatus is provided. The sense amplifier control signal generating circuit includes a timing control unit that models a transmission path of data from a memory cell to a sense amplifier through a bit line and generates a timing control signal at a sensing timing when the sense amplifier starts a sensing operation. A sense amplifier control signal generating unit receives the timing control signal and generates a sense amplifier control signal.
摘要翻译：提供一种半导体存储装置的读出放大器控制信号发生电路。读出放大器控制信号产生电路包括定时控制单元，其通过位线对来自存储单元的数据的传输路径进行建模，并在读出放大器开始感测操作时在感测定时产生定时控制信号。读出放大器控制信号发生单元接收定时控制信号并产生读出放大器控制信号。

4. 发明申请

US20080136484A1 Sense amplifier control signal generating circuit of semiconductor memory apparatus 失效
标题翻译：半导体存储装置的感应放大器控制信号发生电路
公开(公告)号：US20080136484A1
公开(公告)日：2008-06-12
申请号：US11826924
申请日：2007-07-19
申请人： Dae-Suk Kim , Jong Chern Lee
发明人： Dae-Suk Kim , Jong Chern Lee
IPC分类号： H03H11/26
CPC分类号： G11C7/08
摘要： A sense amplifier control signal generating circuit of a semiconductor memory apparatus is provided. The sense amplifier control signal generating circuit includes a timing control unit that models a transmission path of data from a memory cell to a sense amplifier through a bit line and generates a timing control signal at a sensing timing when the sense amplifier starts a sensing operation. A sense amplifier control signal generating unit receives the timing control signal and generates a sense amplifier control signal.
摘要翻译：提供一种半导体存储装置的读出放大器控制信号发生电路。读出放大器控制信号产生电路包括定时控制单元，其通过位线对来自存储单元的数据的传输路径进行建模，并在读出放大器开始感测操作时在感测定时产生定时控制信号。读出放大器控制信号发生单元接收定时控制信号并产生读出放大器控制信号。

5. 发明申请

US20120275246A1 MULTI-TEST APPARATUS AND METHOD FOR SEMICONDUCTOR CHIPS 有权
标题翻译：多功能半导体器件的测试装置和方法
公开(公告)号：US20120275246A1
公开(公告)日：2012-11-01
申请号：US13333487
申请日：2011-12-21
申请人： Dae-Suk Kim
发明人： Dae-Suk Kim
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/12015 , G11C29/1201 , G11C29/14 , G11C29/26 , G11C2029/2602
摘要： An apparatus and method is capable of reducing instantaneously consumed current by allowing write drivers and input buffers not to be simultaneously driven in a multi-test of semiconductor chips. A multi-test apparatus includes an input unit configured to receive data for testing, wherein the data for testing is inputted from a circuit outside of the multi-test apparatus, a plurality of memory banks each including a plurality of memory cells, a plurality of write drivers, corresponding to the respective memory banks, configured to write the test data in the plurality of memory banks, and a write control unit configured to control the plurality of write drivers so that the test data is written in the memory banks in at least two time periods.
摘要翻译：一种装置和方法能够通过允许写入驱动器和输入缓冲器在半导体芯片的多测试中不被同时驱动来减少瞬时消耗的电流。一种多测试装置，包括：被配置为接收用于测试的数据的输入单元，其中，用于测试的数据从多个测试装置外部的电路输入;多个存储体，每个存储体包括多个存储单元;多个存储单元，写入驱动器，对应于相应的存储器组，被配置为将测试数据写入多个存储体中;以及写入控制单元，被配置为控制多个写入驱动器，使得测试数据至少写入存储体两个时期。

6. 发明授权

US08427883B2 Setting circuit and integrated circuit including the same 有权
标题翻译：设置电路和集成电路包括相同
公开(公告)号：US08427883B2
公开(公告)日：2013-04-23
申请号：US12980788
申请日：2010-12-29
申请人： Dae-Suk Kim , Chang-Hyun Lee
发明人： Dae-Suk Kim , Chang-Hyun Lee
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G11C7/109 , G11C29/46
摘要： A setting circuit includes a selection unit configured to select one of a predefined code and an external code in response to a test signal, and a setting information generation unit configured to generate setting information in response to the code selected by the selection unit.
摘要翻译：设置电路包括：响应于测试信号选择预定码和外部码之一的选择单元;以及设置信息生成单元，用于响应于由选择单元选择的代码生成设置信息。

7. 发明授权

US08797814B2 Multi-test apparatus and method for testing a plurailty of semiconductor chips 有权
标题翻译：用于测试半导体芯片的多重测试装置和方法
公开(公告)号：US08797814B2
公开(公告)日：2014-08-05
申请号：US13333487
申请日：2011-12-21
申请人： Dae-Suk Kim
发明人： Dae-Suk Kim
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/12015 , G11C29/1201 , G11C29/14 , G11C29/26 , G11C2029/2602
摘要： An apparatus and method is capable of reducing instantaneously consumed current by allowing write drivers and input buffers not to be simultaneously driven in a multi-test of semiconductor chips. A multi-test apparatus includes an input unit configured to receive data for testing, wherein the data for testing is inputted from a circuit outside of the multi-test apparatus, a plurality of memory banks each including a plurality of memory cells, a plurality of write drivers, corresponding to the respective memory banks, configured to write the test data in the plurality of memory banks, and a write control unit configured to control the plurality of write drivers so that the test data is written in the memory banks in at least two time periods.
摘要翻译：一种装置和方法能够通过允许写入驱动器和输入缓冲器在半导体芯片的多测试中不被同时驱动来减少瞬时消耗的电流。一种多测试装置，包括：被配置为接收用于测试的数据的输入单元，其中，用于测试的数据从多个测试装置外部的电路输入;多个存储体，每个存储体包括多个存储单元;多个存储单元，写入驱动器，对应于相应的存储器组，被配置为将测试数据写入多个存储体中;以及写入控制单元，被配置为控制多个写入驱动器，使得测试数据至少写入存储体两个时期。

8. 发明授权

US08782476B2 Memory and test method for memory 有权
标题翻译：内存和内存的测试方法
公开(公告)号：US08782476B2
公开(公告)日：2014-07-15
申请号：US13338591
申请日：2011-12-28
申请人： Dae-Suk Kim
发明人： Dae-Suk Kim
IPC分类号： G11C29/00 , G11C29/56 , G11C29/48 , G11C29/44 , G11C29/50
CPC分类号： G11C29/56 , G11C29/26 , G11C29/40 , G11C29/44 , G11C29/48 , G11C29/50 , G11C2029/2602
摘要： A test method for a memory having first and second cell arrays, first compressed data obtained by compressing output data of the first cell array and output data of the second cell array is outputted. When the first compressed data represents that a fail exists, output data of one of the first and second cell arrays is locked as normal data, and second compressed data obtained by compressing the normal data and output data of the other of the first and second cell arrays is outputted.
摘要翻译：输出具有第一和第二单元阵列的存储器的测试方法，通过压缩第一单元阵列的输出数据和第二单元阵列的输出数据而获得的第一压缩数据。当第一压缩数据表示存在故障时，第一和第二单元阵列之一的输出数据被锁定为正常数据，并且通过压缩正常数据而获得的第二压缩数据并输出第一和第二单元中的另一个的数据阵列被输出。

9. 发明申请

US20120272108A1 MEMORY AND TEST METHOD FOR MEMORY 有权
标题翻译：存储器的记忆和测试方法
公开(公告)号：US20120272108A1
公开(公告)日：2012-10-25
申请号：US13338591
申请日：2011-12-28
申请人： Dae-Suk Kim
发明人： Dae-Suk Kim
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/56 , G11C29/26 , G11C29/40 , G11C29/44 , G11C29/48 , G11C29/50 , G11C2029/2602
摘要： A test method for a memory having first and second cell arrays, first compressed data obtained by compressing output data of the first cell array and output data of the second cell array is outputted. When the first compressed data represents that a fail exists, output data of one of the first and second cell arrays is locked as normal data, and second compressed data obtained by compressing the normal data and output data of the other of the first and second cell arrays is outputted.
摘要翻译：输出具有第一和第二单元阵列的存储器的测试方法，通过压缩第一单元阵列的输出数据和第二单元阵列的输出数据而获得的第一压缩数据。当第一压缩数据表示存在故障时，第一和第二单元阵列之一的输出数据被锁定为正常数据，并且通过压缩正常数据而获得的第二压缩数据并输出第一和第二单元中的另一个的数据阵列被输出。

10. 发明授权

US07773448B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07773448B2
公开(公告)日：2010-08-10
申请号：US12136487
申请日：2008-06-10
申请人： Dae-Suk Kim , Jin-Hee Cho
发明人： Dae-Suk Kim , Jin-Hee Cho
IPC分类号： G11C8/00
CPC分类号： G11C8/04 , G11C8/12 , G11C8/18
摘要： A semiconductor memory device having multiple banks each including multiple memory blocks arranged in column and row directions. The memory blocks are divided into multiple memory block groups each sharing a corresponding column select signal. The memory blocks belonging to the respective memory block groups are arranged adjacently in the column direction. Multiple global input/output lines are separately connected to the memory block groups of the respective banks to transfer data of the memory blocks belonging to the respective memory block groups in a time division manner.
摘要翻译：一种具有多个存储体的半导体存储器件，每个存储体包括以列和行方向布置的多个存储块。存储器块被分成多个存储器块组，每个存储块组共享相应的列选择信号。属于相应存储块组的存储器块在列方向上相邻布置。多个全局输入/输出线分别连接到各个存储体的存储器块组，以时分方式传送属于各个存储块组的存储块的数据。

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