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1. 发明申请

US20130162311A1 FILTERING CIRCUIT, PHASE IDENTITY DETERMINATION CIRCUIT AND DELAY LOCKED LOOP 有权
标题翻译：滤波电路，相位识别电路和延时锁定环
公开(公告)号：US20130162311A1
公开(公告)日：2013-06-27
申请号：US13607234
申请日：2012-09-07
申请人： Dae-Han KWON , Yong-Ju Kim , Taek-Sang Song
发明人： Dae-Han KWON , Yong-Ju Kim , Taek-Sang Song
IPC分类号： H03L7/06 , H03K5/00
CPC分类号： H03L7/093 , H03L7/0812 , H03L7/235
摘要： A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.
摘要翻译：滤波电路包括时钟选择单元，其被配置为响应于频率信号将具有低于第一时钟的频率的第一时钟或第二时钟作为工作时钟传送;以及滤波器，被配置为滤波输入信号并生成滤波的信号与操作时钟同步。

2. 发明授权

US08867698B2 Counting circuit, delay value quantization circuit, and latency control circuit 有权
标题翻译：计数电路，延迟值量化电路和延时控制电路
公开(公告)号：US08867698B2
公开(公告)日：2014-10-21
申请号：US13620564
申请日：2012-09-14
申请人： Dae-Han Kwon , Yong-Ju Kim , Jae-Il Kim , Taek-Sang Song
发明人： Dae-Han Kwon , Yong-Ju Kim , Jae-Il Kim , Taek-Sang Song
IPC分类号： H03K21/38
CPC分类号： H03K21/38 , H03K21/023
摘要： A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.
摘要翻译：计数电路包括：时钟分割单元，被配置为以预设的分频比划分参考时钟信号并产生分频时钟信号;计数单元，被配置为对分频时钟信号进行计数;计数控制单元，被配置为使计数单元在对应于分频比的使能期间。

3. 发明授权

US08664987B2 Filtering circuit, phase identity determination circuit and delay locked loop 有权
标题翻译：滤波电路，相位识别确定电路和延迟锁定环
公开(公告)号：US08664987B2
公开(公告)日：2014-03-04
申请号：US13607234
申请日：2012-09-07
申请人： Dae-Han Kwon , Yong-Ju Kim , Taek-Sang Song
发明人： Dae-Han Kwon , Yong-Ju Kim , Taek-Sang Song
IPC分类号： H03K5/00
CPC分类号： H03L7/093 , H03L7/0812 , H03L7/235
摘要： A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.
摘要翻译：滤波电路包括时钟选择单元，其被配置为响应于频率信号将具有低于第一时钟的频率的第一时钟或第二时钟作为工作时钟传送;以及滤波器，被配置为对输入信号进行滤波并生成滤波的信号与操作时钟同步。

4. 发明申请

US20130216017A1 COUNTING CIRCUIT, DELAY VALUE QUANTIZATION CIRCUIT, AND LATENCY CONTROL CIRCUIT 有权
公开(公告)号：US20130216017A1
公开(公告)日：2013-08-22
申请号：US13620564
申请日：2012-09-14
申请人： Dae-Han KWON , Yong-Ju Kim , JAE-IL Kim , Taek-Sang Song
发明人： Dae-Han KWON , Yong-Ju Kim , JAE-IL Kim , Taek-Sang Song
IPC分类号： H03K21/00
CPC分类号： H03K21/38 , H03K21/023
摘要： A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.

5. 发明授权

US08253465B2 Semiconductor memory device and method for operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08253465B2
公开(公告)日：2012-08-28
申请号：US13186366
申请日：2011-07-19
申请人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
发明人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
IPC分类号： H03K3/00 , H03K5/13 , H03H11/16
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1072 , G11C7/222 , H03L7/0814
摘要： A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.
摘要翻译：半导体存储器件包括边缘检测器，被配置为接收两对互补时钟以检测时钟的边沿;比较器，被配置为比较边缘检测器的输出信号，以检测同一对的时钟是否具有180度的相位差;以及检测不同对的时钟是否具有90度的相位差，控制信号发生器被配置为根据比较器的输出信号产生用于控制时钟相位的控制信号;以及相位校正器，被配置为校正时钟的相位响应于控制信号。

6. 发明授权

US07986161B2 Termination resistance circuit 有权
标题翻译：端接电阻电路
公开(公告)号：US07986161B2
公开(公告)日：2011-07-26
申请号：US12327294
申请日：2008-12-03
申请人： Jun-Woo Lee , Dae-Han Kwon , Taek-Sang Song
发明人： Jun-Woo Lee , Dae-Han Kwon , Taek-Sang Song
IPC分类号： H03K17/16
CPC分类号： H03K19/018585 , H04L25/0298
摘要： A termination resistance circuit includes a control signal generator for generating a control signal whose logical value changes when a calibration code has a predetermined value, a plurality of parallel resistors which are respectively turned on/off in response to the calibration code, and a resistance value changing unit for changing the total resistance value of the termination resistance circuit in response to the control signal.
摘要翻译：终端电阻电路包括控制信号发生器，用于产生当校准码具有预定值时其逻辑值改变的控制信号，响应于校准码分别导通/关断的多个并联电阻器，以及电阻值改变单元，用于响应于控制信号改变终端电阻电路的总电阻值。

7. 发明授权

US07961026B2 Delay cell and phase locked loop using the same 有权
标题翻译：延迟单元和锁相环使用相同
公开(公告)号：US07961026B2
公开(公告)日：2011-06-14
申请号：US12003676
申请日：2007-12-31
申请人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon
发明人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon
IPC分类号： H03H11/26
CPC分类号： H03L7/0995 , H03K3/0322 , H03K5/133 , H03K2005/00208 , H03K2005/00234 , H03L2207/06
摘要： A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.
摘要翻译：通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。

8. 发明授权

US07929358B2 Data output circuit 有权
标题翻译：数据输出电路
公开(公告)号：US07929358B2
公开(公告)日：2011-04-19
申请号：US12327397
申请日：2008-12-03
申请人： Jun-Woo Lee , Dae-Han Kwon , Taek-Sang Song
发明人： Jun-Woo Lee , Dae-Han Kwon , Taek-Sang Song
IPC分类号： G11C7/10
CPC分类号： G11C7/02 , G11C7/1006 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4096 , G11C2207/107
摘要： A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data.
摘要翻译：数据输出电路包括：串行数据输出单元，用于根据操作模式输出多个并行数据作为串行数据;内部信息输出单元，用于根据操作模式输出内部信息数据;以及缓冲单元，用于接收串行数据数据和内部信息数据通过相同的输入端并缓冲接收到的数据。

9. 发明授权

US07884647B2 Output driver 有权
标题翻译：输出驱动
公开(公告)号：US07884647B2
公开(公告)日：2011-02-08
申请号：US12326990
申请日：2008-12-03
申请人： Kyung-Hoon Kim , Dae-Han Kwon , Taek-Sang Song
发明人： Kyung-Hoon Kim , Dae-Han Kwon , Taek-Sang Song
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528
摘要： There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal.
摘要翻译：提供了一种输出驱动器，其包括配置为响应于数据信号产生主驱动控制信号的预驱动器，配置成响应于主驱动控制信号驱动输出端的主驱动器，辅助驱动控制信号发生器，其被配置为产生具有与数据信号和间隔控制信号对应的激活间隔的辅助驱动控制信号，以及配置为响应于辅助驱动控制信号来驱动输出端子的辅助驱动器。

10. 发明申请

US20090273493A1 Parallel-to-serial converter 有权
标题翻译：并行到串行转换器
公开(公告)号：US20090273493A1
公开(公告)日：2009-11-05
申请号：US12215772
申请日：2008-06-30
申请人： Kyung-Hoon Kim , Dae-Han Kwon , Chang-Kyu Choi , Taek-Sang Song
发明人： Kyung-Hoon Kim , Dae-Han Kwon , Chang-Kyu Choi , Taek-Sang Song
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.
摘要翻译：并行转换器包括：数据输入单元，被配置为通过使用具有不同相位的多个时钟信号来接收多个并行数据;以及并行到串行转换单元，被配置为顺序地选择和输出数据输入单元通过使用与数据输入单元中使用的多个时钟信号具有预定相位差的多个时钟信号。

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