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1. 发明授权

US07495519B2 System and method for monitoring reliability of a digital system 失效
标题翻译：监控数字系统可靠性的系统和方法
公开(公告)号：US07495519B2
公开(公告)日：2009-02-24
申请号：US11742018
申请日：2007-04-30
申请人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic , Hong Hua Song
发明人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic , Hong Hua Song
IPC分类号： G01R23/00 , H03B5/24 , H03K3/03
CPC分类号： G01R31/31937 , G01R31/31725
摘要： System and method are provided for continually monitoring reliability, or aging, of a digital system and for issuing a warning signal if digital system operation degrades past a specified threshold. The technique includes implementing a ring oscillator sensor in association with the digital system, wherein logic and/or device percent composition of the ring oscillator sensor mirrors percent composition thereof within the digital system. Counter logic is coupled to the ring oscillator sensor for converting outputted count signals to an oscillation frequency, and control logic is coupled to the counter logic for periodically evaluating oscillation frequency of the ring oscillator sensor and generating a warning signal indicative of reliability degradation if at least one of: (i) a measured or estimated oscillation frequency is below a warning threshold frequency; or (ii) a measured or estimated rate of change in a difference between measured oscillation frequencies exceeds an acceptable rate of change threshold.
摘要翻译：提供系统和方法用于连续监视数字系统的可靠性或老化，并且如果数字系统操作降低到指定的阈值以上，则发出警告信号。该技术包括实现与数字系统相关联的环形振荡器传感器，其中环形振荡器传感器的逻辑和/或设备百分比组成反映数字系统内的其组成的百分比。计数器逻辑耦合到环形振荡器传感器，用于将输出的计数信号转换为振荡频率，并且控制逻辑耦合到计数器逻辑，用于周期性评估环形振荡器传感器的振荡频率，并产生指示可靠性降级的警告信号，如果至少以下之一：（i）测量或估计的振荡频率低于警告阈值频率; 或者（ii）所测量的振荡频率之间的测量或估计的变化率超过可接受的变化率阈值。

2. 发明授权

US08094706B2 Frequency-based, active monitoring of reliability of a digital system 有权
标题翻译：基于频率，主动监控数字系统的可靠性
公开(公告)号：US08094706B2
公开(公告)日：2012-01-10
申请号：US11733318
申请日：2007-04-10
申请人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic , Hong Hua Song
发明人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic , Hong Hua Song
IPC分类号： H04B3/46 , H04B17/00 , H04Q1/20
CPC分类号： G06F11/008
摘要： Method, system and article of manufacture are provided for continually monitoring reliability, or aging, of a digital system and for issuing a warning signal if digital system operation degrades to or past a specified threshold. The technique includes periodically determining a maximum frequency of operation of the digital system, and generating a warning signal indicative of a reliability degradation of the digital system if at least one of: (i) a measured or estimated maximum frequency of operation of the digital system is below a warning threshold frequency of operation of the digital system, wherein the warning threshold frequency is greater than or equal to a manufacturer specified minimum frequency of operation for the digital system; or (ii) a rate of change in the difference between measured maximum frequencies of operation of the digital system exceeds an acceptable rate of change threshold for the digital system.
摘要翻译：提供了方法，系统和制造品，用于连续监视数字系统的可靠性或老化，并且如果数字系统操作降低到或超过指定阈值，则发出警告信号。该技术包括周期性地确定数字系统的最大操作频率，以及产生指示数字系统的可靠性劣化的警告信号，如果以下至少一个：（i）数字系统的测量或估计的最大操作频率低于数字系统的警告阈值操作频率，其中警告阈值频率大于或等于制造商规定的数字系统的最小操作频率; 或者（ii）数字系统的测量的最大操作频率之间的差异的变化率超过数字系统的可接受的变化率阈值。

3. 发明申请

US20080177506A1 METHOD AND SYSTEM FOR TESTING PROCESSOR CORES 有权
标题翻译：用于测试加工器的方法和系统
公开(公告)号：US20080177506A1
公开(公告)日：2008-07-24
申请号：US11624329
申请日：2007-01-18
申请人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G06F15/00
CPC分类号： G06F11/24 , G01R31/3004 , G01R31/31721 , G01R31/318505
摘要： Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于测试多核处理器芯片结构。单个处理器核心电源电压通过控制每个核心的单独电源来提供，在一个方面，以确保一个或多个核心以按照一个或多个性能规格的时钟速率运行。在一个示例中，提供给第一处理核心的第一电源电压与提供给第二处理核心的第二核心电源电压不同，两个核心都遵循参考时钟速率规范操作。核心电源电压可以从通过逐渐提高或降低第一电源电压而导出的有序离散电源电压中选择，任选地，其中所选择的电源电压还使得核能够在另一性能规格内操作。

4. 发明授权

US07912670B2 Testing processor cores 有权
标题翻译：测试处理器内核
公开(公告)号：US07912670B2
公开(公告)日：2011-03-22
申请号：US12128075
申请日：2008-05-28
申请人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
IPC分类号： G01R31/00
CPC分类号： G06F11/24 , G01R31/3004 , G01R31/31721 , G01R31/318505
摘要： Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于测试多核处理器芯片结构。单个处理器核心电源电压通过控制每个核心的单独电源来提供，在一个方面，以确保一个或多个核心以按照一个或多个性能规格的时钟速率运行。在一个示例中，提供给第一处理核心的第一电源电压与提供给第二处理核心的第二核心电源电压不同，两个核心都遵循参考时钟速率规范操作。核心电源电压可以从通过逐渐提高或降低第一电源电压而导出的有序离散电源电压中选择，任选地，其中所选择的电源电压还使得核能够在另一性能规格内操作。

5. 发明申请

US20080262777A1 SYSTEM FOR TESTING PROCESSOR CORES 有权
标题翻译：测试加工器系统
公开(公告)号：US20080262777A1
公开(公告)日：2008-10-23
申请号：US12128075
申请日：2008-05-28
申请人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G01R31/00 , G06F15/00
CPC分类号： G06F11/24 , G01R31/3004 , G01R31/31721 , G01R31/318505
摘要： Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于测试多核处理器芯片结构。单个处理器核心电源电压通过控制每个核心的单独电源来提供，在一个方面，以确保一个或多个核心以按照一个或多个性能规格的时钟速率运行。在一个示例中，提供给第一处理核心的第一电源电压与提供给第二处理核心的第二核心电源电压不同，两个核心都遵循参考时钟速率规范操作。核心电源电压可以从通过逐渐提高或降低第一电源电压而导出的有序离散电源电压中选择，任选地，其中所选择的电源电压还使得核能够在另一性能规格内操作。

6. 发明授权

US07853808B2 Independent processor voltage supply 有权
标题翻译：独立处理器电压供应
公开(公告)号：US07853808B2
公开(公告)日：2010-12-14
申请号：US11624333
申请日：2007-01-18
申请人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： Systems, methods and program codes are provided for selectively adjusting multi-core processor chip structure individual processor core power supply voltages through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. Nominal power supply voltage is supplied to a first processing core, and a second core power supply voltage greater or lower than the nominal power supply voltage is supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. The second power supply voltage may be selected from ordered discrete supply voltages derived by progressively lowering the nominal supply voltage, optionally wherein the selected supply voltage also enables the second core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于通过控制每个核心的单个电源来选择性地调整多核处理器核心电源电压的多核处理器芯片结构，以确保一个或多个内核按照一个时钟速率运行或更多性能规格。标称电源电压被提供给第一处理核心，并且大于或低于标称电源电压的第二核心电源电压被提供给第二处理核心，两个核心都遵守参考时钟速率规范。第二电源电压可以从通过逐渐降低标称电源电压而导出的有序的离散电源电压中选择，可选地，其中所选择的电源电压还使得第二磁芯能够在另一性能规范内操作。

7. 发明授权

US07418368B2 Method and system for testing processor cores 有权
标题翻译：用于测试处理器内核的方法和系统
公开(公告)号：US07418368B2
公开(公告)日：2008-08-26
申请号：US11624329
申请日：2007-01-18
申请人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
IPC分类号： G06F15/00
CPC分类号： G06F11/24 , G01R31/3004 , G01R31/31721 , G01R31/318505
摘要： Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于测试多核处理器芯片结构。单个处理器核心电源电压通过控制每个核心的单独电源来提供，在一个方面，以确保一个或多个核心以按照一个或多个性能规格的时钟速率运行。在一个示例中，提供给第一处理核心的第一电源电压与提供给第二处理核心的第二核心电源电压不同，两个核心都遵循参考时钟速率规范操作。核心电源电压可以从通过逐渐提高或降低第一电源电压而导出的有序离散电源电压中选择，任选地，其中所选择的电源电压还使得核能够在另一性能规格内操作。

8. 发明申请

US20080178023A1 METHOD AND SYSTEM FOR INDEPENDENT PROCESSOR VOLTAGE SUPPLY 有权
标题翻译：独立处理器电压供应方法与系统
公开(公告)号：US20080178023A1
公开(公告)日：2008-07-24
申请号：US11624333
申请日：2007-01-18
申请人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： Systems, methods and program codes are provided for selectively adjusting multi-core processor chip structure individual processor core power supply voltages through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. Nominal power supply voltage is supplied to a first processing core, and a second core power supply voltage greater or lower than the nominal power supply voltage is supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. The second power supply voltage may be selected from ordered discrete supply voltages derived by progressively lowering the nominal supply voltage, optionally wherein the selected supply voltage also enables the second core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于通过控制每个核心的单个电源来选择性地调整多核处理器核心电源电压的多核处理器芯片结构，以确保一个或多个内核按照一个时钟速率运行或更多性能规格。标称电源电压被提供给第一处理核心，并且大于或低于标称电源电压的第二核心电源电压被提供给第二处理核心，两个核心都遵守参考时钟速率规范。第二电源电压可以从通过逐渐降低标称电源电压而导出的有序的离散电源电压中选择，可选地，其中所选择的电源电压还使得第二磁芯能够在另一性能规范内操作。

9. 发明授权

US07821110B2 Circuit structures and methods with BEOL layer(s) configured to block electromagnetic interference 有权
标题翻译： BEOL层的电路结构和方法被配置为阻止电磁干扰
公开(公告)号：US07821110B2
公开(公告)日：2010-10-26
申请号：US11747342
申请日：2007-05-11
申请人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , Choongyeun Cho
发明人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , Choongyeun Cho
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： Back end of line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic interference. One such BEOL circuit structure includes one or more semiconductor substrates supporting one or more integrated circuits, and one or more BEOL layers disposed over the semiconductor substrate(s). At least one BEOL layer includes a conductive pattern defined at least partially by a plurality of elements arrayed in a first direction and a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in at least one of the first and second directions to block electromagnetic interference of a particular wavelength from passing therethrough. In one implementation, a first conductive pattern of a first BEOL layer polarizes electromagnetic interference, and a second conductive pattern of a second BEOL layer blocks the polarized electromagnetic interference.
摘要翻译：提供后端（BEOL）电路结构和方法来阻止外部来源或内部产生的电磁干扰。一种这样的BEOL电路结构包括支撑一个或多个集成电路的一个或多个半导体衬底以及设置在半导体衬底之上的一个或多个BEOL层。至少一个BEOL层包括至少部分地由在第一方向和第二方向排列的多个元件至少部分地限定的导电图案。多个元件的大小和位置在第一和第二方向中的至少一个方向上，以阻止特定波长的电磁干扰通过。在一个实施方案中，第一BEOL层的第一导电图案使电磁干扰偏振，并且第二BEOL层的第二导电图案阻挡极化的电磁干扰。

10. 发明申请

US20080136697A1 METHOD AND SYSTEM FOR RANDOM NUMBER GENERATOR WITH RANDOM SAMPLING 失效
标题翻译：随机采样随机数发生器的方法与系统
公开(公告)号：US20080136697A1
公开(公告)日：2008-06-12
申请号：US11608264
申请日：2006-12-08
申请人： Choongyeun Cho , Dae Ik Kim , Jonghae Kim , Moon J. Kim
发明人： Choongyeun Cho , Dae Ik Kim , Jonghae Kim , Moon J. Kim
IPC分类号： G06F7/58
CPC分类号： G06F7/588
摘要： In a random number generator, a first converter converts a first analog noise signal into a random digital clock signal and a second converter samples a second analog noise signal asynchronous to the first analog noise signal in response to the random digital clock signal and generates a random digital number stream. In one aspect, a random number generator output block samples the second converter random digital number stream in response to the random digital clock signal and generates a random number generator block output. In another aspect a pseudo noise source state machine generates the random digital clock signal in response to a first seed generated from the first analog noise signal, a second seed from process variation digital amplifier, and a past machine state.
摘要翻译：在随机数发生器中，第一转换器将第一模拟噪声信号转换成随机数字时钟信号，并且第二转换器响应于随机数字时钟信号对与第一模拟噪声信号异步的第二模拟噪声信号进行采样，并产生随机数数字数字流。一方面，随机数发生器输出块响应于随机数字时钟信号对第二转换器随机数字数字流进行采样，并产生随机数发生器块输出。在另一方面，伪噪声源状态机响应于从第一模拟噪声信号产生的第一种子，来自过程变化数字放大器的第二种子和过去的机器状态，产生随机数字时钟信号。

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