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1. 发明申请

US20160077904A1 INTEGRATED CIRCUIT AND METHOD OF DETECTING A DATA INTEGRITY ERROR 有权
标题翻译：集成电路和检测数据完整性错误的方法
公开(公告)号：US20160077904A1
公开(公告)日：2016-03-17
申请号：US14483262
申请日：2014-09-11
申请人： DIRK WENDEL , MICHAEL ROHLEDER , ROLF SCHLAGENHAFT
发明人： DIRK WENDEL , MICHAEL ROHLEDER , ROLF SCHLAGENHAFT
IPC分类号： G06F11/07
CPC分类号： G06F11/079 , G06F11/0736 , G06F11/0751 , G06F11/0772
摘要： An integrated circuit comprises a write bus coupled to a register for storing control data. A storage unit is arranged to store reference signature data encoding a reference collective state of the register. First logic circuitry generates actual signature data encoding the actual collective state of the register. Second logic circuitry is coupled to the storage unit, receives the actual signature data and compares the actual signature data with the reference signature data. The second logic circuitry comprises an alert output to provide an alert signal in response to the comparison identifying a difference between the actual signature data and the reference signature data, thereby ensuring detection of a data integrity error in respect of the register. An alert inhibitor comprises a control input and is responsive to the control input and arranged to inhibit selectively onward propagation of the alert signal from the alert output.
摘要翻译：集成电路包括耦合到用于存储控制数据的寄存器的写总线。存储单元被布置为存储编码寄存器的参考集合状态的参考签名数据。第一逻辑电路生成编码寄存器的实际集体状态的实际签名数据。第二逻辑电路耦合到存储单元，接收实际签名数据并将实际签名数据与参考签名数据进行比较。第二逻辑电路包括警报输出，以响应于比较来识别实际签名数据和参考签名数据之间的差异来提供警报信号，从而确保检测关于该寄存器的数据完整性错误。警报抑制器包括控制输入并且响应于控制输入并被布置成禁止警报信号从警报输出中选择性地向前传播。

2. 发明申请

US20160132070A1 OSCILLATOR CIRCUIT AND METHOD OF GENERATING A CLOCK SIGNAL 有权
标题翻译：振荡器电路和产生时钟信号的方法
公开(公告)号：US20160132070A1
公开(公告)日：2016-05-12
申请号：US14899170
申请日：2013-07-04
申请人： Hubert BODE , Dirk WENDEL
发明人： HUBERT BODE , DIRK WENDEL
IPC分类号： G06F1/08 , H03K3/023
CPC分类号： G06F1/08 , H03K3/023 , H03K3/0231
摘要： An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.
摘要翻译：一种振荡器电路，包括用于产生时钟信号的触发器和用于将参考电压与在第一电容器的第一周期期间充电的第一电容器两端的电压进行比较的两个比较器，以及跨越第二电容器的电压在时钟信号的第二周期期间被充电提供了用于消除任一比较器中任何偏移的影响的装置。这是通过在输出频率的每个周期反转比较器的输入来实现的。因此，将在一个周期上增加时钟周期的比较器中的偏移将使下一个周期的周期减少相同的量。作为最终结果，无论比较器中有任何偏移漂移，两个时钟周期的时间段将保持不变。

3. 发明申请

US20160037186A1 METHOD AND VIDEO SYSTEM FOR FREEZE-FRAME DETECTION 有权
标题翻译：用于冻结框架检测的方法和视频系统
公开(公告)号：US20160037186A1
公开(公告)日：2016-02-04
申请号：US14445718
申请日：2014-07-29
申请人： DIRK WENDEL , JOACHIM FADER , STEPHAN HERRMANN , WILHARD CHRISTOPHORUS VON WENDORFF
发明人： DIRK WENDEL , JOACHIM FADER , STEPHAN HERRMANN , WILHARD CHRISTOPHORUS VON WENDORFF
IPC分类号： H04N19/89 , H04N19/66 , H04N19/46
CPC分类号： H04N19/89
摘要： A method for detecting a freeze-frame condition comprises receiving a sequence of images from at least one digital device; selectively encoding a first subset of the sequence of images using a first coding scheme that causes an adjustment to an image characteristic of the selected images being encoded; selectively encoding a second subset of the sequence of images using a second coding scheme; storing the first encoded subset and second encoded subset; retrieving the stored first encoded subset and second encoded subset; selectively decoding the first subset of the selected images using the first coding scheme and selectively decoding the second subset of the selected images using the second coding scheme to re-create the sequence of images. A freeze-frame condition in the re-created sequence of images is identifiable based on a plurality of decoded images being different with respect to the image characteristic across multiple decoded image frames.
摘要翻译：一种用于检测冻结帧状况的方法包括从至少一个数字设备接收一系列图像; 使用导致对被编码的所选择的图像的图像特征进行调整的第一编码方案来选择性地编码图像序列的第一子集; 使用第二编码方案选择性地编码图像序列的第二子集; 存储第一编码子集和第二编码子集; 检索所存储的第一编码子集和第二编码子集; 使用第一编码方案选择性地解码所选图像的第一子集，并且使用第二编码方案选择性地解码所选图像的第二子集以重新创建图像序列。基于多个解码图像相对于跨多个解码图像帧的图像特征而不同的图像重新创建序列中的冻结帧条件是可识别的。

4. 发明申请

US20150281742A1 CIRCUIT ARRANGEMENT AND METHOD FOR PROCESSING A DIGITAL VIDEO STREAM AND FOR DETECTING A FAULT IN A DIGITAL VIDEO STREAM, DIGITAL VIDEO SYSTEM AND COMPUTER READABLE PROGRAM PRODUCT 有权
标题翻译：用于处理数字视频流并用于检测数字视频流，数字视频系统和计算机可读程序产品中的故障的电路布置和方法
公开(公告)号：US20150281742A1
公开(公告)日：2015-10-01
申请号：US14224167
申请日：2014-03-25
申请人： MICHAEL ANDREAS STAUDENMAIER , VICTOR-HUGO OSORNIO LOPEZ , DIRK WENDEL
发明人： MICHAEL ANDREAS STAUDENMAIER , VICTOR-HUGO OSORNIO LOPEZ , DIRK WENDEL
IPC分类号： H04N19/89 , H04N7/18 , H04N19/65
CPC分类号： H04N7/183 , H04N19/89
摘要： The present invention relates to a circuit arrangement for processing a digital video stream, the circuit arrangement comprising: an input interface for receiving a digital video stream, a processing circuit which is arranged to process the digital video stream, a hang-up detecting circuit for detecting a fault in the processed digital video stream, the hang-up detecting circuit comprising: a checksum generating circuit which is arranged to generate checksums for the frames of the processed digital video stream, a memory for storing generated checksums and an analyzing device arranged to compare a currently generated checksum to a plurality of corresponding checksums of preceding frames stored in the memory and to generate an error signal if at least one predefined amount of compared checksums are matching. The present invention also relates to a digital video system, a method for processing a digital video stream and a computer readable program product.
摘要翻译：本发明涉及一种用于处理数字视频流的电路装置，所述电路装置包括：用于接收数字视频流的输入接口，被配置为处理数字视频流的处理电路，一个挂起检测电路，用于检测所处理的数字视频流中的故障，所述上挂检测电路包括：校验和产生电路，被配置为产生经处理的数字视频流的帧的校验和，用于存储生成的校验和的存储器和布置成将当前生成的校验和与存储在存储器中的先前帧的多个对应校验和进行比较，并且如果至少一个预定量的比较校验和匹配，则生成错误信号。本发明还涉及数字视频系统，用于处理数字视频流的方法和计算机可读程序产品。

5. 发明申请

US20160071228A1 DATA LOGGING SYSTEM AND METHOD 有权
标题翻译：数据记录系统及方法
公开(公告)号：US20160071228A1
公开(公告)日：2016-03-10
申请号：US14479456
申请日：2014-09-08
申请人： DIRK WENDEL , STEPHAN HERRMANN , MICHAEL ANDREAS STAUDENMAIER
发明人： DIRK WENDEL , STEPHAN HERRMANN , MICHAEL ANDREAS STAUDENMAIER
IPC分类号： G06T1/00 , G06K9/00
CPC分类号： G06T1/0007 , G06K9/00926 , G07C5/0866 , G07C5/0891 , G08B13/19676
摘要： A data logging system for logging input data received from a data source is described. The data logging system has a data storage memory. A data input is arranged to repeatedly receive input data having a temporal input data resolution. A write controller is arranged to write newly received input data as received via the data input into the data storage memory. The writing comprises writing the newly received input data at the temporal input data resolution. The writing comprises keeping recent data at the temporal input data resolution in the data storage memory, and overwriting part of old data with newly received input data while keeping another part of the old data in the data storage memory at lower data resolution.
摘要翻译：描述用于记录从数据源接收的输入数据的数据记录系统。数据记录系统具有数据存储存储器。数据输入被布置为重复地接收具有时间输入数据分辨率的输入数据。写入控制器被布置成经由输入到数据存储器中的数据来写入接收的新接收的输入数据。写入包括以时间输入数据分辨率写入新接收的输入数据。该写入包括在数据存储存储器中保持最新数据处于时间输入数据分辨率，并且用新接收的输入数据覆盖旧数据的一部分，同时将数据存储存储器中的另一部分旧数据保持在较低的数据分辨率。

6. 发明申请

US20160034398A1 CACHE-COHERENT MULTIPROCESSOR SYSTEM AND A METHOD FOR DETECTING FAILURES IN A CACHE-COHERENT MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：高速缓存多媒体处理系统和一种用于检测高速缓存多媒体系统中的故障的方法
公开(公告)号：US20160034398A1
公开(公告)日：2016-02-04
申请号：US14445237
申请日：2014-07-29
申请人： DIRK WENDEL , OLIVER BIBEL , JOACHIM FADER , WILHARD CHRISTOPHORUS VON WENDORFF
发明人： DIRK WENDEL , OLIVER BIBEL , JOACHIM FADER , WILHARD CHRISTOPHORUS VON WENDORFF
IPC分类号： G06F12/08
摘要： A cache-coherent multiprocessor system comprising processing units, a shared memory resource accessible by the processing units, the shared memory resource being divided into at least one shared region, at least one first region, and at least one second region, a first cache, a second cache, a coherency unit, and a monitor unit, wherein the monitor unit is adapted to generate an error signal, when the coherency unit affects the at least one first region due to a memory access from the second processing unit and/or when the coherency unit affects the at least one second region due to a memory access from the first processing unit, and a method for detecting failures in a such a cache-coherent multiprocessor system.
摘要翻译：一种高速缓存一致的多处理器系统，包括处理单元，由处理单元可访问的共享存储器资源，共享存储器资源被划分为至少一个共享区域，至少一个第一区域和至少一个第二区域，第一高速缓存，第二高速缓存，一致性单元和监视器单元，其中当所述一致性单元由于来自所述第二处理单元的存储器访问而影响所述至少一个第一区域时和/或何时所述监视单元适于产生错误信号相关性单元由于来自第一处理单元的存储器访问而影响至少一个第二区域，以及用于检测这种高速缓存相关多处理器系统中的故障的方法。

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