专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP0455376B1 Method for manufacturing an integrated circuit comprising a high-precision resistor 失效
标题翻译：一种用于与高精密电阻制造集成电路过程
公开(公告)号：EP0455376B1
公开(公告)日：1997-10-15
申请号：EP91303388.2
申请日：1991-04-16
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Zetterlund, Bjorn K.A.
IPC分类号： H01L21/82 , H01L29/86 , H01C17/06
CPC分类号： H01L29/66166 , H01L21/8238 , H01L27/0629

2. 发明公开

EP0455376A2 Method for manufacturing an integrated circuit comprising a high-precision resistor 失效
标题翻译：一种用于制造具有高精密电阻的集成电路过程。
公开(公告)号：EP0455376A2
公开(公告)日：1991-11-06
申请号：EP91303388.2
申请日：1991-04-16
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Zetterlund, Bjorn K.A.
IPC分类号： H01L21/82 , H01L29/86 , H01C17/06
CPC分类号： H01L29/66166 , H01L21/8238 , H01L27/0629
摘要： A precision resistor (11) is formed in an integrated circuit by a diffused region created at the same time as transistor source/drain regions (18, 24). In a CMOS process, this N-type resistor region is formed in an N-well (16), as is used for P-channel transistors. The resistor is formed using a deposited oxide layer (46) as a mask, and this oxide layer is also used to create sidewall spacers (24, 25) for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas (26, 27) over the source/drain regions, self-aligned with the gates, and the silicide is also used for contact areas (38) for the resistor. The value of the resistor is defined by the width of the deposited oxide layer left as a mask, but this does not require any critical alignment steps.
摘要翻译：精密电阻器（11）是由在同一时间作为晶体管源/漏区（18，24）创建的扩散区域形成为集成电路。在CMOS工艺中，该N型电阻区域是形成在N阱（16），作为用于P沟道晶体管。该电阻通过沉积氧化物层（46）作为掩模形成的，因此该氧化物层被用来创建用于晶体管栅极侧壁间隔物（24，25）。侧壁间隔件在创建自对准硅化物区域（26，27）在该源/漏区，与栅极自对准的使用，因此硅化物被用于接触区（38），用于电阻器。电阻器的值是通过留下作为掩模的沉积的氧化物层的宽度限定，但是这并不需要任何严格的对准步骤。

3. 发明公开

EP0455376A3 Method for manufacturing an integrated circuit comprising a high-precision resistor 失效
标题翻译：用于制造包括高精度电阻器的集成电路的方法
公开(公告)号：EP0455376A3
公开(公告)日：1995-03-15
申请号：EP91303388.2
申请日：1991-04-16
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Zetterlund, Bjorn K.A.
IPC分类号： H01L21/82 , H01L29/86 , H01C17/06
CPC分类号： H01L29/66166 , H01L21/8238 , H01L27/0629
摘要： A precision resistor (11) is formed in an integrated circuit by a diffused region created at the same time as transistor source/drain regions (18, 24). In a CMOS process, this N-type resistor region is formed in an N-well (16), as is used for P-channel transistors. The resistor is formed using a deposited oxide layer (46) as a mask, and this oxide layer is also used to create sidewall spacers (24, 25) for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas (26, 27) over the source/drain regions, self-aligned with the gates, and the silicide is also used for contact areas (38) for the resistor. The value of the resistor is defined by the width of the deposited oxide layer left as a mask, but this does not require any critical alignment steps.
摘要翻译：精密电阻器（11）通过与晶体管源极/漏极区（18,24）同时产生的扩散区在集成电路中形成。在CMOS工艺中，该N型电阻器区域形成在N阱（16）中，如用于P沟道晶体管的那样。使用沉积的氧化物层（46）作为掩模形成电阻器，并且该氧化物层还用于形成用于晶体管栅极的侧壁间隔物（24,25）。侧壁间隔物用于在源极/漏极区域上方产生自对准硅化物区域（26,27），与栅极自对准，并且硅化物也用于电阻器的接触区域（38）。电阻的值由沉积的氧化层的宽度定义为掩膜，但这不需要任何关键的对准步骤。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式