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1. 发明授权

EP0430501B1 System and method for drawing antialiased polygons 失效
标题翻译：系统和方法不失真绘制多边形
公开(公告)号：EP0430501B1
公开(公告)日：1999-02-03
申请号：EP90312472.5
申请日：1990-11-15
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Kelleher, Brian Michael
IPC分类号： G06T15/50
CPC分类号： G06T11/40 , G06T15/503

2. 发明公开

EP0431776A3 Method of drawing a line segment in a graphics system 失效
标题翻译：在图形系统中绘制线段的方法
公开(公告)号：EP0431776A3
公开(公告)日：1992-11-19
申请号：EP90312474.1
申请日：1990-11-15
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Kelleher, Brian Michael
IPC分类号： G06F15/72 , G09G5/20
CPC分类号： G06T11/203
摘要： A method is provided for generating pixel color information for use in producing an image of a line segment on a graphics display screen, the method comprising the steps of: denoting at least one planar region of the display screen that encompasses the line segment; assigning respective intensity values for at least three selected pixels encompassed by the at least one planar region; assigning respective color values for the at least three selected pixels; and interpolating respective final color values for each respective pixel encompassed by the at least one planar region based upon the respective assigned intensity values and the respective assigned color values.

3. 发明公开

EP0430500A2 System and method for atomic access to an input/output device with direct memory access 失效
标题翻译：系统和原子论访问方法将Eingaben- /输出设备与直接存储器访问。
公开(公告)号：EP0430500A2
公开(公告)日：1991-06-05
申请号：EP90312471.7
申请日：1990-11-15
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Kelleher, Brian Michael , Chow, Shu-Shia
IPC分类号： G06F15/16 , G06F9/46
CPC分类号： G06F15/167 , G06F3/14
摘要： A system (30) for atomic access to an I/O device with DMA includes a CPU (32) connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics subsystem (45). The interface (44) is connected by bus (46) to graphics processor (48). In this system, graphics subsystem (45) is an I/O device, and atomic access to it is required. Command packet interface (44) to the graphics subsystem (45) transfers geometry and graphics context information from main memory (40) to the graphics subsystem (45). For such transfers, an application writes a list of commands to a physically contiguous locked-down memory buffer (47) in its own address space. Since the system (30) has DMA, the buffer (47) resides in the main memory system (40). When the buffer (47) is full, the CPU (32) tells the graphics subsystem (45), via a read from an I/O address on the graphics subsystem (45), that it should begin a transfer of the command packet. Status of the operation is returned as a result of the I/O read transaction. After initiating the command packet transfer, the graphics subsystem (45) parses the packet and executes the appropriate operations atomically.
摘要翻译：一种用于原子访问在I / O设备与DMA系统（30）包括由总线（36）连接到一个浮点处理器（FPU）（34）的CPU（32）。所述CPU（32）通过系统总线（38）到一个随机存取存储器（RAM）（40）连接，高速缓冲存储器（42）和接口（44）在图形子系统（45）。接口（44）通过总线（46），连接到图形处理器（48）。在这个系统中，图形子系统（45）是一种I / O设备，并且需要它的原子访问。命令分组接口（44），以图形子系统（45）从主存储器（40）传送的几何形状和图形上下文信息提供给图形子系统（45）。对于寻求转移到应用程序写入命令的列表，以在其自己的地址空间中的物理上连续的锁定的存储器缓冲器（47）。由于该系统（30）具有DMA，缓冲器（47）驻留在主存储器系统（40）。当缓冲器（47）是满的，则CPU（32）讲述通过从读图形子系统（45）在（45）上的图形子系统的I / O地址没有它shoulderstand开始传送所述命令包的。操作的状态被返回作为我的结果/ O读事务。发起命令分组传输之后，图形子系统（45）解析所述分组并自动执行适当的操作。

4. 发明公开

EP0430501A3 System and method for drawing antialiased polygons 失效
标题翻译：绘制抗生素多糖的系统和方法
公开(公告)号：EP0430501A3
公开(公告)日：1993-03-24
申请号：EP90312472.5
申请日：1990-11-15
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Kelleher, Brian Michael
IPC分类号： G06F15/72
CPC分类号： G06T11/40 , G06T15/503
摘要： A system (30) draws antialiased polygons. A CPU (32) is connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a 32-bit system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics sub-system (45). The interface (44) is connected by bus (46) to graphics processor (48). The graphics processor (48) is connected by 120-bit graphics bus (50) to frame buffer (52). The frame buffer (52) is connected to a video digital to analog converter (DAC) (54) by bus (56). The DAC (54) is connected to video display (58) by line (60). The graphics processor (48) use a technique known as supersampling to combat the effects of aliasing. In aliased mode, the graphics processor (48) use 16 array sites to sample 16 pixels (72). When drawing a polygon or line in antialiased mode, the graphics processor (48) uses the 16 sites to sample at 16 locations (120) within a single pixel (72). The antialiasing is done by determining what proportion of the locations (120) within each pixel (72) are within the polygon and setting a color of each pixel (72) on the basis of the proportion.

5. 发明公开

EP0430501A2 System and method for drawing antialiased polygons 失效
标题翻译：系统和Verfahren zumunverfälschtenPolygonenzeichnen。
公开(公告)号：EP0430501A2
公开(公告)日：1991-06-05
申请号：EP90312472.5
申请日：1990-11-15
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Kelleher, Brian Michael
IPC分类号： G06F15/72
CPC分类号： G06T11/40 , G06T15/503
摘要： A system (30) draws antialiased polygons. A CPU (32) is connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a 32-bit system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics sub-system (45). The interface (44) is connected by bus (46) to graphics processor (48). The graphics processor (48) is connected by 120-bit graphics bus (50) to frame buffer (52). The frame buffer (52) is connected to a video digital to analog converter (DAC) (54) by bus (56). The DAC (54) is connected to video display (58) by line (60). The graphics processor (48) use a technique known as supersampling to combat the effects of aliasing. In aliased mode, the graphics processor (48) use 16 array sites to sample 16 pixels (72). When drawing a polygon or line in antialiased mode, the graphics processor (48) uses the 16 sites to sample at 16 locations (120) within a single pixel (72). The antialiasing is done by determining what proportion of the locations (120) within each pixel (72) are within the polygon and setting a color of each pixel (72) on the basis of the proportion.
摘要翻译：系统（30）绘制抗锯齿多边形。 CPU（32）通过总线（36）连接到浮点处理器（FPU）（34）。 CPU（32）通过32位系统总线（38）连接到图形子系统（45）中的随机存取存储器（RAM）（40），高速缓冲存储器（42）和接口（44）。接口（44）通过总线（46）连接到图形处理器（48）。图形处理器（48）通过120位图形总线（50）连接到帧缓冲器（52）。帧缓冲器（52）通过总线（56）连接到视频数/模转换器（DAC）（54）。 DAC（54）通过线（60）连接到视频显示器（58）。图形处理器（48）使用称为超级采样的技术来抵抗混叠的影响。在混叠模式下，图形处理器（48）使用16个阵列位点来采样16像素（72）。当以抗锯齿模式绘制多边形或线时，图形处理器（48）使用16个位点在单个像素（72）内的16个位置（120）进行采样。通过确定每个像素（72）内的位置（120）在多边形内的比例以及基于比例来设置每个像素（72）的颜色来完成抗锯齿。

6. 发明授权

EP0430502B1 A method for simultaneous initialization of a double buffer and a frame buffer 失效
标题翻译：双缓冲器和帧缓冲器的同时初始化
公开(公告)号：EP0430502B1
公开(公告)日：1998-01-14
申请号：EP90312473.3
申请日：1990-11-15
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Kelleher, Brian Michael , Hussain, Zahid
IPC分类号： G06T1/00 , G09G1/16
CPC分类号： G09G5/399 , G06T15/405 , G09G5/363 , G09G2360/122 , G09G2360/126

7. 发明公开

EP0430500A3 System and method for atomic access to an input/output device with direct memory access 失效
标题翻译：用于原始访问具有直接存储器访问的输入/输出设备的系统和方法
公开(公告)号：EP0430500A3
公开(公告)日：1992-03-04
申请号：EP90312471.7
申请日：1990-11-15
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Kelleher, Brian Michael , Chow, Shu-Shia
IPC分类号： G06F15/16 , G06F9/46
CPC分类号： G06F15/167 , G06F3/14
摘要： A system (30) for atomic access to an I/O device with DMA includes a CPU (32) connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics subsystem (45). The interface (44) is connected by bus (46) to graphics processor (48). In this system, graphics subsystem (45) is an I/O device, and atomic access to it is required. Command packet interface (44) to the graphics subsystem (45) transfers geometry and graphics context information from main memory (40) to the graphics subsystem (45). For such transfers, an application writes a list of commands to a physically contiguous locked-down memory buffer (47) in its own address space. Since the system (30) has DMA, the buffer (47) resides in the main memory system (40). When the buffer (47) is full, the CPU (32) tells the graphics subsystem (45), via a read from an I/O address on the graphics subsystem (45), that it should begin a transfer of the command packet. Status of the operation is returned as a result of the I/O read transaction. After initiating the command packet transfer, the graphics subsystem (45) parses the packet and executes the appropriate operations atomically.

8. 发明公开

EP0430502A2 A method for simultaneous initialization of a double buffer and a frame buffer 失效
标题翻译： Gleichzeitiges Initialisierungsverfahren von Doppelpuffer und Rasterpuffer。
公开(公告)号：EP0430502A2
公开(公告)日：1991-06-05
申请号：EP90312473.3
申请日：1990-11-15
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Kelleher, Brian Michael , Hussain, Zahid
IPC分类号： G06F15/72 , G09G1/16
CPC分类号： G09G5/399 , G06T15/405 , G09G5/363 , G09G2360/122 , G09G2360/126
摘要： A method is provided for generating pixel color information for use in producing an image of a line segment on a graphics display screen, the method comprising the steps of: denoting at least one planar region of the display screen that encompasses the line segment; assigning respective intensity values for at least three selected pixels encompassed by the at least one planar region; assigning respective color values for the at least three selected pixels; and interpolating respective final color values for each respective pixel encompassed by the at least one planar region based upon the respective assigned intensity values and the respective assigned color values.
摘要翻译：提供了一种用于生成用于在图形显示屏幕上产生线段的图像的像素颜色信息的方法，所述方法包括以下步骤：表示包含线段的显示屏幕的至少一个平面区域; 为由所述至少一个平面区域包围的至少三个所选择的像素分配各个强度值; 为所述至少三个所选择的像素分配各个颜色值; 以及基于各自分配的强度值和相应的分配的颜色值，内插由所述至少一个平面区域包围的每个相应像素的各个最终颜色值。

9. 发明授权

EP0430500B1 System and method for atomic access to an input/output device with direct memory access 失效
标题翻译：系统和原子论访问方法将Eingaben- /输出设备与直接存储器访问
公开(公告)号：EP0430500B1
公开(公告)日：1996-09-11
申请号：EP90312471.7
申请日：1990-11-15
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Kelleher, Brian Michael , Chow, Shu-Shia
IPC分类号： G06F15/16 , G06F9/46
CPC分类号： G06F15/167 , G06F3/14

10. 发明公开

EP0430502A3 A method for simultaneous initialization of a double buffer and a frame buffer 失效
标题翻译：一种双缓冲区和帧缓冲器同时初始化的方法
公开(公告)号：EP0430502A3
公开(公告)日：1993-06-02
申请号：EP90312473.3
申请日：1990-11-15
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Kelleher, Brian Michael , Hussain, Zahid
IPC分类号： G06F15/72 , G09G1/16
CPC分类号： G09G5/399 , G06T15/405 , G09G5/363 , G09G2360/122 , G09G2360/126
摘要： A method is provided for generating pixel color information for use in producing an image of a line segment on a graphics display screen, the method comprising the steps of: denoting at least one planar region of the display screen that encompasses the line segment; assigning respective intensity values for at least three selected pixels encompassed by the at least one planar region; assigning respective color values for the at least three selected pixels; and interpolating respective final color values for each respective pixel encompassed by the at least one planar region based upon the respective assigned intensity values and the respective assigned color values.

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