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1. 发明公开

EP0145530A3 Arrangement for providing data signals for a data display system 失效
标题翻译：为数据显示系统提供数据信号的安排
公开(公告)号：EP0145530A3
公开(公告)日：1989-07-26
申请号：EP84402086.7
申请日：1984-10-17
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Di Nitto, Robert Salvatore , Porcher, Thomas Courtenay , Eng, John Wai , Namias, Charles , Hughes, David Bruce
IPC分类号： G09G1/16
CPC分类号： G09G5/393
摘要： @ The present invention includes a microprocessor (15) which acts to generate rasters of its signals from its read only memory (ROM), thereby forming character representations of groups of coded signals, such as ASCII coded signals, coming from a main data processing device. The rasters of bit signals are temporarily stored in a buffer (23) which at a subsequent time transmits, in parallel, groups of said bit signals to a bit map memory (33) through logic circuitry. The group, or block, transfer of these bit signals in parallel occurs during horizontal or vertical blank periods. The parallel transfer during the blank periods provides part of the basis for acceleration of the transfer of data to a display device as compared with the prior art. In addition, the microprocessor provides address information signals to a graphic display controller (19), which in turn provides starting addresses for the location of the bit signals. In addition, a bit map memory device is employed to provide pixel information to a CRT display device (51) to create the characters to be displayed.

2. 发明授权

EP0145529B1 Split screen smooth scrolling arrangement 有权
标题翻译：分屏幕平滑滚动装置
公开(公告)号：EP0145529B1
公开(公告)日：1992-08-19
申请号：EP84402085.9
申请日：1984-10-17
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Di Nitto, Robert Salvatore , Porcher, Thomas Courtenay , Eng, John Wai
IPC分类号： G09G1/16
CPC分类号： G09G5/346

3. 发明公开

EP0145529A2 Split screen smooth scrolling arrangement 有权
标题翻译：用于数据的分布式屏幕上的周期运动。
公开(公告)号：EP0145529A2
公开(公告)日：1985-06-19
申请号：EP84402085.9
申请日：1984-10-17
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Di Nitto, Robert Salvatore , Porcher, Thomas Courtenay , Eng, John Wai
IPC分类号： G09G1/16
CPC分类号： G09G5/346
摘要： The present invention is employed in a system which has a bit map memory connected to a CRT display device and the CRT display device cab display a fixed region of information and a scrollable region of information. In a preffered embodiment, the system uses a graphic display control circuit (19) to change starting addresses and length ending values of the fixed and scrollable regions in the bit map memory. By changing the starting address one scan line per frame, without any actual transfer of data in memory, from one location to another location, the present system effects a «smooth» scroll. The system is able to scroll upward and downward. The system uses logic circuitry to load an off screen segment of the bit map memory with additional scrollable information, so that (in an upward scroll load) as a top line of the scrollable information region is no longer displayed, new information will be displayed at the bottom line of said scrollable region. On the other hand during a downward scroll, a bottom line of information on the scrollable region of the screen will fade out and new information is added, from the off screen region, of the bit map memory to provide information for a new top line. In addition the system has the ability to reorganize the information in the bit map memory in the event the size or location of the fixed region is to be altered.

4. 发明公开

EP0145529A3 Split screen smooth scrolling arrangement 有权
标题翻译：分屏幕平滑滚动装置
公开(公告)号：EP0145529A3
公开(公告)日：1989-07-19
申请号：EP84402085.9
申请日：1984-10-17
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Di Nitto, Robert Salvatore , Porcher, Thomas Courtenay , Eng, John Wai
IPC分类号： G09G1/16
CPC分类号： G09G5/346
摘要： The present invention is employed in a system which has a bit map memory connected to a CRT display device and the CRT display device cab display a fixed region of information and a scrollable region of information. In a preffered embodiment, the system uses a graphic display control circuit (19) to change starting addresses and length ending values of the fixed and scrollable regions in the bit map memory. By changing the starting address one scan line per frame, without any actual transfer of data in memory, from one location to another location, the present system effects a «smooth» scroll. The system is able to scroll upward and downward. The system uses logic circuitry to load an off screen segment of the bit map memory with additional scrollable information, so that (in an upward scroll load) as a top line of the scrollable information region is no longer displayed, new information will be displayed at the bottom line of said scrollable region. On the other hand during a downward scroll, a bottom line of information on the scrollable region of the screen will fade out and new information is added, from the off screen region, of the bit map memory to provide information for a new top line. In addition the system has the ability to reorganize the information in the bit map memory in the event the size or location of the fixed region is to be altered.

5. 发明公开

EP0145530A2 Arrangement for providing data signals for a data display system 失效
标题翻译：装置，用于为一个数据显示系统采购数据。
公开(公告)号：EP0145530A2
公开(公告)日：1985-06-19
申请号：EP84402086.7
申请日：1984-10-17
申请人： DIGITAL EQUIPMENT CORPORATION
发明人： Di Nitto, Robert Salvatore , Porcher, Thomas Courtenay , Eng, John Wai , Namias, Charles , Hughes, David Bruce
IPC分类号： G09G1/16
CPC分类号： G09G5/393
摘要： @ The present invention includes a microprocessor (15) which acts to generate rasters of its signals from its read only memory (ROM), thereby forming character representations of groups of coded signals, such as ASCII coded signals, coming from a main data processing device. The rasters of bit signals are temporarily stored in a buffer (23) which at a subsequent time transmits, in parallel, groups of said bit signals to a bit map memory (33) through logic circuitry. The group, or block, transfer of these bit signals in parallel occurs during horizontal or vertical blank periods. The parallel transfer during the blank periods provides part of the basis for acceleration of the transfer of data to a display device as compared with the prior art. In addition, the microprocessor provides address information signals to a graphic display controller (19), which in turn provides starting addresses for the location of the bit signals. In addition, a bit map memory device is employed to provide pixel information to a CRT display device (51) to create the characters to be displayed.

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