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1. 发明申请

US20110084327A1 3-D ELECTRICALLY PROGRAMMABLE AND ERASABLE SINGLE-TRANSISTOR NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译： 3-D电可编程和可擦除单晶非易失性半导体存储器件
公开(公告)号：US20110084327A1
公开(公告)日：2011-04-14
申请号：US12880039
申请日：2010-09-10
申请人： DE YUAN XIAO , Gary Chen , Roger Lee
发明人： DE YUAN XIAO , Gary Chen , Roger Lee
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7885 , H01L21/28273 , H01L29/42324 , H01L29/66825
摘要： A non-volatile memory device includes a source region, a drain region, and a channel region therebetween. The channel region has a length extending from the source region to the drain region and a channel width in the direction perpendicular to the channel length direction. The device includes a floating gate positioned between the source and the drain in the channel length direction. The width of the floating gate is less than the channel width. A control gate covers a top surface and a side surface of the floating gate. The control gate also overlies an entirety of the channel region. Erasure of the cell is accomplished by Fowler-Nordheim tunneling from the floating gate to the control gate. Programming is accomplished by electrons migrating through an electron concentration gradient from a channel region underneath the control gate into a channel region underneath the floating gate and then injecting into the floating gate.
摘要翻译：非易失性存储器件包括源极区，漏极区和它们之间的沟道区。沟道区域具有从源极区域到漏极区域的长度以及与沟道长度方向垂直的方向的沟道宽度。该器件包括在沟道长度方向上位于源极和漏极之间的浮动栅极。浮动栅极的宽度小于通道宽度。控制栅极覆盖浮动栅极的顶表面和侧表面。控制门也覆盖整个通道区域。通过从浮动门到控制门的Fowler-Nordheim隧道实现对电池的擦除。编程是通过电子从电子浓度梯度从控制栅极下方的沟道区域迁移到浮动栅极下方的沟道区域中，然后注入到浮动栅极中来实现的。

2. 发明申请

US20130029483A1 METHOD AND SYSTEM FOR FORMING CONDUCTIVE BUMPING WITH COPPER INTERCONNECTION 有权
标题翻译：用于形成具有铜互连的导电保护的方法和系统
公开(公告)号：US20130029483A1
公开(公告)日：2013-01-31
申请号：US13645448
申请日：2012-10-04
申请人： DE YUAN XIAO , Guo Qing Chen
发明人： DE YUAN XIAO , Guo Qing Chen
IPC分类号： H01L21/768
CPC分类号： H01L23/53295 , H01L23/53238 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05572 , H01L2224/05644 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/11 , H01L2224/1147 , H01L2224/11912 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2224/45124 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/15788 , H01L2924/00 , H01L2224/48 , H01L2224/05552 , H01L2924/013
摘要： A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a metal material. The metal material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the metal material.
摘要翻译：一种用于制造具有与衬底导电连接的一个或多个铜互连的集成电路系统的方法包括沉积和构图第一介电层以形成第一通孔，并用铜材料填充第一通孔穿过第一介电层。该方法还包括沉积和图案化与第一介电层接触的第二介电层以形成第二通孔，并形成扩散阻挡层。此外，该方法包括在扩散阻挡层上沉积和图案化光致抗蚀剂层，并且用金属材料至少部分地填充第二通孔。金属材料通过扩散阻挡层与铜材导电连接。该方法还包括去除不被金属材料覆盖的光致抗蚀剂和扩散阻挡层。

3. 发明申请

US20120088363A1 METHOD AND SYSTEM FOR FORMING CONDUCTIVE BUMPING WITH COPPER INTERCONNECTION 有权
标题翻译：用于形成具有铜互连的导电保护的方法和系统
公开(公告)号：US20120088363A1
公开(公告)日：2012-04-12
申请号：US13269538
申请日：2011-10-07
申请人： DE YUAN XIAO , Guo Qing Chen
发明人： DE YUAN XIAO , Guo Qing Chen
IPC分类号： H01L21/768
CPC分类号： H01L23/53295 , H01L23/53238 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05572 , H01L2224/05644 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/11 , H01L2224/1147 , H01L2224/11912 , H01L2224/13 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2224/45124 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/15788 , H01L2924/00 , H01L2224/48 , H01L2224/05552 , H01L2924/013
摘要： A method for making an integrated circuit system with one or more copper interconnects that are conductively connected with a substrate includes depositing and patterning a first dielectric layer to form a first via and filling the first via through the first dielectric layer with a copper material. The method further includes depositing and patterning a second dielectric layer in contact with the first dielectric layer to form a second via, and forming a diffusion barrier layer. Moreover, the method includes depositing and patterning a photoresist layer on the diffusion barrier layer, and at least partially filling the second via with a gold material. The gold material is conductively connected to the copper material through the diffusion barrier layer. The method further includes removing the photoresist and the diffusion barrier layer not covering by the gold material. Additionally, the method includes conductively connecting the gold material with the substrate.
摘要翻译：一种用于制造具有与衬底导电连接的一个或多个铜互连的集成电路系统的方法包括沉积和构图第一介电层以形成第一通孔，并用铜材料填充第一通孔穿过第一介电层。该方法还包括沉积和图案化与第一介电层接触的第二介电层以形成第二通孔，并形成扩散阻挡层。此外，该方法包括在扩散阻挡层上沉积和图案化光致抗蚀剂层，并且用金材料至少部分地填充第二通孔。金材料通过扩散阻挡层与铜材导电连接。该方法还包括去除未被金材料覆盖的光致抗蚀剂和扩散阻挡层。此外，该方法包括将金材料与衬底导电连接。

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