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1. 发明申请

US20130055190A1 COMPUTING DEVICE AND METHOD FOR CHECKING DESIGN OF PRINTED CIRCUIT BOARD LAYOUT FILE 失效
标题翻译：打印电路板布局文件设计的计算装置及方法
公开(公告)号：US20130055190A1
公开(公告)日：2013-02-28
申请号：US13523874
申请日：2012-06-14
申请人： DAN-CHEN WU , SHOU-KUO HSU , CHUN-JEN CHEN
发明人： DAN-CHEN WU , SHOU-KUO HSU , CHUN-JEN CHEN
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/78
摘要： A computing device reads a printed circuit board (PCB) layout file from a storage device. The PCB layout file includes arrangement information of signal lines, power lines, and power through-holes arranged on a PCB. Furthermore, the computing device sets a reference distance between a selected power through-hole and a neighboring signal line, and searches for one or more line segments of one or more signal lines where the a distance between each of the one or more line segment and the selected power through-hole is less than the reference distance.
摘要翻译：计算设备从存储设备读取印刷电路板（PCB）布局文件。 PCB布局文件包括布置在PCB上的信号线，电源线和电源通孔的布置信息。此外，计算装置设置所选功率通孔和相邻信号线之间的参考距离，并且搜索一个或多个信号线的一个或多个线段，其中，所述一个或多个线段中的每一个之间的距离和所选功率通孔小于参考距离。

2. 发明申请

US20120297356A1 COMPUTING DEVICE AND METHOD FOR INSPECTING LAYOUT OF PRINTED CIRCUIT BOARD 失效
标题翻译：用于检查印刷电路板布局的计算装置和方法
公开(公告)号：US20120297356A1
公开(公告)日：2012-11-22
申请号：US13213072
申请日：2011-08-18
申请人： DAN-CHEN WU , SHOU-KUO HSU , CHENG-HSIEN LEE , CHUN-JEN CHEN
发明人： DAN-CHEN WU , SHOU-KUO HSU , CHENG-HSIEN LEE , CHUN-JEN CHEN
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： In a method for inspecting the layout of a printed circuit board (PCB), a component to be checked is determined from an electronic layout diagram of the PCB, and a power transmission line which may be serving that component is selected. The layout diagram is checked to determine whether the component is connected to the power transmission line, and further checked to determine whether more than one ground pins of the component is connected to the power transmission line. Vias that are shared by two or more ground pins of the component are determined if more than one ground pin is connected to the power transmission line. Shared vias are marked on the layout diagram.
摘要翻译：在用于检查印刷电路板（PCB）的布局的方法中，从PCB的电子布局图确定要检查的部件，并且可以选择可用于该部件的输电线。检查布局图以确定组件是否连接到电力传输线，并进一步检查以确定组件的多个接地引脚是否连接到电力传输线。如果多个接地引脚连接到电力传输线，则确定由组件的两个或更多个接地引脚共享的通孔。共享通孔在布局图上标出。

3. 发明申请

US20120278784A1 ELECTRONIC DEVICE AND METHOD FOR CHECKING LAYOUT OF PRINTED CIRCUIT BOARD 失效
标题翻译：电子设备和检查印刷电路板布局的方法
公开(公告)号：US20120278784A1
公开(公告)日：2012-11-01
申请号：US13315291
申请日：2011-12-09
申请人： DAN-CHEN WU , SHOU-KUO HSU , CHENG-HSIEN LEE , CHUN-JEN CHEN
发明人： DAN-CHEN WU , SHOU-KUO HSU , CHENG-HSIEN LEE , CHUN-JEN CHEN
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： In a method for checking layout of a printed circuit board (PCB) using an electronic device, a power line is selected from a layout diagram of the PCB. The method searches for one or more signal lines which are overlapping with the selected power line from the layout diagram of the PCB. The method further locates attribute data of the searched signal lines and the selected power line in the layout diagram of the PCB, and displays the attribute data of the searched signal lines and the selected power line on a display device of the electronic device.
摘要翻译：在使用电子设备检查印刷电路板（PCB）的布局的方法中，从PCB的布局图中选择电力线。该方法从PCB的布局图搜索与所选择的电力线重叠的一条或多条信号线。该方法进一步在PCB的布局图中定位搜索到的信号线和所选电力线的属性数据，并将所搜索的信号线和所选电力线的属性数据显示在电子设备的显示装置上。

4. 发明申请

US20110106481A1 SYSTEM AND METHOD FOR CHECKING GROUND VIAS OF A CONTROLLER CHIP OF A PRINTED CIRCUIT BOARD 失效
标题翻译：印刷电路板控制芯片的接地检查系统及方法
公开(公告)号：US20110106481A1
公开(公告)日：2011-05-05
申请号：US12700747
申请日：2010-02-05
申请人： HSIEN-CHUAN LIANG , SHEN-CHUN LI , CHUN-JEN CHEN , SHOU-KUO HSU , YUNG-CHIEH CHEN , WEN-LAING TSENG
发明人： HSIEN-CHUAN LIANG , SHEN-CHUN LI , CHUN-JEN CHEN , SHOU-KUO HSU , YUNG-CHIEH CHEN , WEN-LAING TSENG
IPC分类号： G06F19/00 , G01R31/00
CPC分类号： G01R31/2806 , G01R31/2834
摘要： A system and method for checking a ground via of control chips of a printed circuit board (PCB) provides a graphical user interface (GUI) displaying a layout of the PCB. The control chip has a plurality of ground pins. The computer searches for signal path routing of each ground pin and ground vias along each signal path routing of each ground pin. If there are any ground vias having the same absolute coordinates, the computer determines that the ground vias are shared by more than one ground pin.
摘要翻译：用于检查印刷电路板（PCB）的控制芯片的接地通路的系统和方法提供了显示PCB布局的图形用户界面（GUI）。控制芯片具有多个接地引脚。计算机沿每个接地引脚的每个信号路径路由搜索每个接地引脚和接地通孔的信号路径路由。如果有任何接地通孔具有相同的绝对坐标，则计算机确定接地通孔由多个接地引脚共用。

5. 发明申请

US20100321910A1 PRINTED CIRCUIT BOARD 失效
标题翻译：印刷电路板
公开(公告)号：US20100321910A1
公开(公告)日：2010-12-23
申请号：US12497709
申请日：2009-07-06
申请人： SHOU-KUO HSU , CHUN-JEN CHEN
发明人： SHOU-KUO HSU , CHUN-JEN CHEN
IPC分类号： H05K7/00
CPC分类号： H05K1/0231 , H05K1/0253 , H05K1/112 , H05K3/429 , H05K2201/0969 , H05K2201/10545 , H05K2201/10689
摘要： A printed circuit board includes a first signal layer, a first reference layer, a second reference layer, and a second signal layer. An integrated circuit mounted on the first signal layer includes a power supply terminal connected to a first power supply via. The second signal layer includes a filter and a power supply wire. The filter includes a power terminal connected to the first power supply via, and a ground terminal connected to the second reference layer. The first power supply via is connected to the first reference layer through the power supply wire and a second power supply via. A void defined in the second reference layer is at least partially vertically overlapping with the power supply wire, and enables the first reference layer to function as a reference plane for the power supply wire, to increase impedance of the power supply wire.
摘要翻译：印刷电路板包括第一信号层，第一参考层，第二参考层和第二信号层。安装在第一信号层上的集成电路包括连接到第一电源通孔的电源端子。第二信号层包括滤波器和电源线。滤波器包括连接到第一电源通孔的电源端子和连接到第二参考层的接地端子。第一电源通孔通过电源线和第二电源通孔连接到第一参考层。限定在第二参考层中的空隙至少部分地与电源线垂直重叠，并且使得第一参考层能够用作电源线的参考平面，以增加电源线的阻抗。

6. 发明申请

US20090242244A1 PRINTED CIRCUIT BOARD 失效
标题翻译：印刷电路板
公开(公告)号：US20090242244A1
公开(公告)日：2009-10-01
申请号：US12126748
申请日：2008-05-23
申请人： SHOU-KUO HSU , CHUN-JEN CHEN
发明人： SHOU-KUO HSU , CHUN-JEN CHEN
IPC分类号： H05K1/00
CPC分类号： H05K1/0245 , H05K1/0298 , H05K2201/09236 , H05K2201/09336
摘要： An exemplary PCB includes a first reference layer, a first signal layer, and a second signal layer in that order. A first differential pair is arranged in the first signal layer in an edge-coupled structure referencing the first reference layer. A second differential pair is arranged in the second signal layer in edge-coupled structure. A first ground part and a second ground part are symmetrically arranged at opposite sides of the second differential pair in the second signal layer. The first differential pair is arranged above the first ground part and a projection of the first differential pair onto the second signal layer having an area coincident with the first ground part. The second differential pair references the first and second ground parts.
摘要翻译：示例性的PCB包括第一参考层，第一信号层和第二信号层。第一差分对以参考第一参考层的边缘耦合结构布置在第一信号层中。第二差分对以边缘耦合结构布置在第二信号层中。第一接地部分和第二接地部分对称地布置在第二信号层中的第二差分对的相对侧。第一差分对布置在第一接地部分的上方，并且第一差分对的突起与具有与第一接地部分重合的区域的第二信号层上。第二差分对参考第一和第二接地部分。

7. 发明申请

US20110093831A1 SYSTEM AND METHOD FOR ANALYZING TEMPERATURE RISE OF A PRINTED CIRCUIT BOARD 失效
标题翻译：用于分析印刷电路板温度升高的系统和方法
公开(公告)号：US20110093831A1
公开(公告)日：2011-04-21
申请号：US12790857
申请日：2010-05-31
申请人： TSUNG-SHENG HUANG , CHUN-JEN CHEN , DUEN-YI HO , WEI-CHIEH CHOU , HSIEN-CHUAN LIANG , SHOU-KUO HSU
发明人： TSUNG-SHENG HUANG , CHUN-JEN CHEN , DUEN-YI HO , WEI-CHIEH CHOU , HSIEN-CHUAN LIANG , SHOU-KUO HSU
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A system and method that can analyze a temperature rise of a printed circuit board (PCB). The system and method receives attribute parameters of the PCB from an input device, and generates a temperature rise formula according to the received attribute parameters. Additionally, the system and method calculates a temperature rise of a local area surrounding each component on the PCB according to the temperature rise formula.
摘要翻译：可以分析印刷电路板（PCB）的温度升高的系统和方法。该系统和方法从输入装置接收PCB的属性参数，并根据接收的属性参数生成温升公式。另外，该系统和方法根据温升公式计算PCB上每个部件周围的局部区域的温度上升。

8. 发明申请

US20110051793A1 SYSTEM AND METHOD FOR EVALUATING PERFORMANCE OF A MIMO ANTENNA SYSTEM 失效
标题翻译：用于评估MIMO天线系统性能的系统和方法
公开(公告)号：US20110051793A1
公开(公告)日：2011-03-03
申请号：US12633895
申请日：2009-12-09
申请人： PO-CHUAN HSIEH , CHUN-JEN CHEN , CHIEN-HUNG LIU , YU-CHANG PAI , SHOU-KUO HSU
发明人： PO-CHUAN HSIEH , CHUN-JEN CHEN , CHIEN-HUNG LIU , YU-CHANG PAI , SHOU-KUO HSU
IPC分类号： H04B17/00
CPC分类号： H04B17/0085 , H04B17/21 , H04B17/23 , H04B17/327 , H04L1/0668
摘要： A performance evaluation system for a multiple-input multiple-output (MIMO) antenna system receives simulation parameters from an input device, and simulates a MIMO antenna system accordingly. A method, also provided, further evaluates performance of the simulated MIMO antenna system when a series of radio frequency (RF) signals are transmitted through the MIMO antenna system, and displays a performance analysis result of the MIMO antenna system on a display device for evaluation of the performance of the simulated MIMO antenna system.
摘要翻译：用于多输入多输出（MIMO）天线系统的性能评估系统从输入设备接收模拟参数，并相应地模拟MIMO天线系统。还提供了一种方法，当通过MIMO天线系统传输一系列射频（RF）信号时，进一步评估模拟MIMO天线系统的性能，并且在用于评估的显示装置上显示MIMO天线系统的性能分析结果的模拟MIMO天线系统的性能。

9. 发明申请

US20090278633A1 EQUALIZER AND CONNECTOR INCLUDING THE SAME 有权
标题翻译：均衡器和连接器包括它们
公开(公告)号：US20090278633A1
公开(公告)日：2009-11-12
申请号：US12168541
申请日：2008-07-07
申请人： CHUN-JEN CHEN , SHOU-KUO HSU
发明人： CHUN-JEN CHEN , SHOU-KUO HSU
IPC分类号： H04B3/14
CPC分类号： H04L27/01 , H05K1/025 , H05K1/181 , H05K2201/10015 , H05K2201/10022 , H05K2201/10189
摘要： An equalizer includes a first resistor and a capacitor connected in parallel. The positive terminal of the capacitor is connected to a signal transmission line on a blah printed circuit board. The negative terminal of the capacitor is connected to ground through a second resistor. A connector including the equalizer and a printed circuit board including the connector are also provided.
摘要翻译：均衡器包括并联连接的第一电阻器和电容器。电容器的正极端子连接到blah印刷电路板上的信号传输线。电容器的负极通过第二个电阻连接到地。还提供了包括均衡器的连接器和包括连接器的印刷电路板。

10. 发明申请

US20090102535A1 CLOCK SIGNAL CIRCUIT FOR MULTIPLE LOADS 审中-公开
标题翻译：多个负载的时钟信号电路
公开(公告)号：US20090102535A1
公开(公告)日：2009-04-23
申请号：US11967036
申请日：2007-12-29
申请人： CHUN-JEN CHEN , YU-CHANG PAI , SHOU-KUO HSU
发明人： CHUN-JEN CHEN , YU-CHANG PAI , SHOU-KUO HSU
IPC分类号： G06F1/04
CPC分类号： G06F1/06 , G06F1/10
摘要： A clock signal circuit for multiple loads includes a clock generator and M loads. The clock generator includes N clock generator pins which output clock signals having a same frequency. The N clock generator pins are all connected to a connection point. The connection point is connected to M loads via M transmitting lines respectively, wherein M is larger than N, M and N each is an integer greater than 2.
摘要翻译：用于多个负载的时钟信号电路包括时钟发生器和M个负载。时钟发生器包括输出具有相同频率的时钟信号的N个时钟发生器引脚。 N个时钟发生器引脚都连接到连接点。连接点分别通过M个发送线路连接到M个负载，其中M大于N，M和N分别为大于2的整数。

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