专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070032035A1 Container capacitor structure and method of formation thereof 失效
公开(公告)号：US20070032035A1
公开(公告)日：2007-02-08
申请号：US11545252
申请日：2006-10-10
申请人： D. Durcan , Trung Doan , Roger Lee , Fernando Gonzalez , Er-Xuan Ping
发明人： D. Durcan , Trung Doan , Roger Lee , Fernando Gonzalez , Er-Xuan Ping
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10817 , H01L27/10852 , H01L27/10888 , H01L28/65 , Y10S257/905
摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

2. 发明申请

US20060006445A1 Container capacitor structure and method of formation thereof 失效
公开(公告)号：US20060006445A1
公开(公告)日：2006-01-12
申请号：US11217742
申请日：2005-09-01
申请人： D. Durcan , Trung Doan , Roger Lee , Fernando Gonzalez , Er-Xuan Ping
发明人： D. Durcan , Trung Doan , Roger Lee , Fernando Gonzalez , Er-Xuan Ping
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10817 , H01L27/10852 , H01L27/10888 , H01L28/65 , Y10S257/905
摘要： Container capacitor structure and method of construction. An etch mask and etch are used to expose portions of an exterior surface of an electrode (“bottom electrodes”) of the structure. The etch provides a recess between proximal pairs of container capacitor structures, which is available for forming additional capacitance. A capacitor dielectric and top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Surface area common to both the first electrode and second electrodes is increased over using only the interior surface, providing additional capacitance without decreasing spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.

3. 发明申请

US20060115957A1 Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces 有权
标题翻译：微型工件加工设备及控制材料沉积在微型工件上的方法
公开(公告)号：US20060115957A1
公开(公告)日：2006-06-01
申请号：US11327794
申请日：2006-01-06
申请人： Cem Basceri , Trung Doan , Ronald Weimer , Kevin Beaman , Lyle Breiner , Lingyi Zheng , Er-Xuan Ping , Demetrius Sarigiannis , David Kubista
发明人： Cem Basceri , Trung Doan , Ronald Weimer , Kevin Beaman , Lyle Breiner , Lingyi Zheng , Er-Xuan Ping , Demetrius Sarigiannis , David Kubista
IPC分类号： H01L21/76 , H01L21/20 , H01L21/302
CPC分类号： C23C16/45527 , C23C16/34 , C23C16/45546
摘要： The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.
摘要翻译：本公开提供了用于在批次的微特征工件上沉积材料中有用的方法和装置。一个实施方案提供了一种方法，其中一定量的第一前体气体以第一封壳压力被引入外壳。当以第一流速引入吹扫气体时，外壳内的压力降低到第二封闭压力。第二外壳压力可接近或等于处理系统在第一流量下的稳态基础压力。在降低压力之后，吹扫气体流量可以增加到第二流量，并且外壳压力可以增加到第三外壳压力。此后，第二前体气体的流动可以在第四封闭压力下以外壳内的压力引入; 第三外壳压力理想地在第四外壳压力的约10％内。

4. 发明申请

US20060057800A1 Methods for treating pluralities of discrete semiconductor substrates 有权
公开(公告)号：US20060057800A1
公开(公告)日：2006-03-16
申请号：US11206340
申请日：2005-08-17
申请人： Trung Doan , Lyle Breiner , Er-Xuan Ping , Lingyi Zheng
发明人： Trung Doan , Lyle Breiner , Er-Xuan Ping , Lingyi Zheng
IPC分类号： H01L21/8238
CPC分类号： H01L21/0228 , C23C16/0236 , C23C16/0245 , C23C16/45546 , C23C16/54 , C30B25/02 , H01L21/02046 , H01L21/0214 , H01L21/02142 , H01L21/02164 , H01L21/0217 , H01L21/02175 , H01L21/02211 , H01L21/02326 , H01L21/28562 , H01L21/3144 , H01L21/31604 , H01L21/31683 , H01L21/3185 , H01L21/76841 , H01L21/76856 , H01L21/76888
摘要： The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

5. 发明申请

US20050164466A1 Methods for forming small-scale capacitor structures 失效
标题翻译：形成小型电容器结构的方法
公开(公告)号：US20050164466A1
公开(公告)日：2005-07-28
申请号：US10767298
申请日：2004-01-28
申请人： Lingyi Zheng , Trung Doan , Lyle Breiner , Er-Xuan Ping , Kevin Beaman , Ronald Weimer , Cem Basceri , David Kubista
发明人： Lingyi Zheng , Trung Doan , Lyle Breiner , Er-Xuan Ping , Kevin Beaman , Ronald Weimer , Cem Basceri , David Kubista
IPC分类号： H01L21/02 , H01L21/314 , H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , H01L21/3141 , H01L27/10852 , H01L28/60 , H01L28/84
摘要： The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50Å.
摘要翻译：本公开提供小尺寸电容器（例如，DRAM电容器）以及形成这种电容器的方法。一个示例性实施例提供了一种制造电容器的方法，该电容器包括顺序地形成第一电极，电介质层和第二电极。可以通过以下方式形成至少一个电极：a）使两个前体反应以第一沉积速率沉积第一导电层，以及b）通过沉积一个前体的前体层以第二较低沉积速率沉积第二导电层至少一层单层，并将该前体层暴露于另一种前体以形成纳米层反应产物。第二导电层可以与电介质层接触并具有不大于约50埃的厚度。

6. 发明申请

US20050059261A1 Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces 失效
标题翻译：微型工件加工设备及控制材料沉积在微型工件上的方法
公开(公告)号：US20050059261A1
公开(公告)日：2005-03-17
申请号：US10665099
申请日：2003-09-17
申请人： Cem Basceri , Trung Doan , Ronald Weimer , Kevin Beaman , Lyle Breiner , Lingyi Zheng , Er-Xuan Ping , Demetrius Sarigiannis , David Kubista
发明人： Cem Basceri , Trung Doan , Ronald Weimer , Kevin Beaman , Lyle Breiner , Lingyi Zheng , Er-Xuan Ping , Demetrius Sarigiannis , David Kubista
IPC分类号： C23C16/34 , H01L21/31
CPC分类号： C23C16/45527 , C23C16/34 , C23C16/45546
摘要： The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.
摘要翻译：本公开提供了用于在批次的微特征工件上沉积材料中有用的方法和装置。一个实施方案提供了一种方法，其中一定量的第一前体气体以第一封壳压力被引入外壳。当以第一流速引入吹扫气体时，外壳内的压力降低到第二封闭压力。第二外壳压力可接近或等于处理系统在第一流量下的稳态基础压力。在降低压力之后，吹扫气体流量可以增加到第二流量，并且外壳压力可以增加到第三外壳压力。此后，第二前体气体的流动可以在第四封闭压力下以外壳内的压力引入; 第三外壳压力理想地在第四外壳压力的约10％内。

7. 发明申请

US20050042824A1 Semiconductor structures, DRAM cells and electronic systems 失效
标题翻译：半导体结构，DRAM单元和电子系统
公开(公告)号：US20050042824A1
公开(公告)日：2005-02-24
申请号：US10945774
申请日：2004-09-20
申请人： Shenlin Chen , Trung Doan , Guy Blalock , Lyle Breiner , Er-Xuan Ping
发明人： Shenlin Chen , Trung Doan , Guy Blalock , Lyle Breiner , Er-Xuan Ping
IPC分类号： H01L21/02 , H01L21/20 , H01L21/8242 , H01L23/58
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/84 , Y10S438/964
摘要： The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.
摘要翻译：本发明包括形成坚固的含半导体的表面的方法。在衬底上形成第一半导体层，并且在第一半导体层上形成第二半导体层。随后，在第二半导体层上形成第三半导体层，并且在第三半导体层上形成含半导体的种子。将种子退火以形成坚固的含半导体的表面。第一，第二和第三半导体层是公共堆叠的一部分，并且可以在电容器结构的存储节点内一起使用。本发明还包括包括粗糙表面的半导体结构。坚固的表面可以是例如坚固的硅。

8. 发明申请

US20060228857A1 DRAM cells 失效
标题翻译： DRAM单元
公开(公告)号：US20060228857A1
公开(公告)日：2006-10-12
申请号：US11449433
申请日：2006-06-07
申请人： Shenlin Chen , Trung Doan , Guy Blalock , Lyle Breiner , Er-Xuan Ping
发明人： Shenlin Chen , Trung Doan , Guy Blalock , Lyle Breiner , Er-Xuan Ping
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/84 , Y10S438/964
摘要： The invention includes a method of forming a rugged semiconductor-containing surface. A first semiconductor layer is formed over a substrate, and a second semiconductor layer is formed over the first semiconductor layer. Subsequently, a third semiconductor layer is formed over the second semiconductor layer, and semiconductor-containing seeds are formed over the third semiconductor layer. The seeds are annealed to form the rugged semiconductor-containing surface. The first, second and third semiconductor layers are part of a common stack, and can be together utilized within a storage node of a capacitor construction. The invention also includes semiconductor structures comprising rugged surfaces. The rugged surfaces can be, for example, rugged silicon.
摘要翻译：本发明包括形成坚固的含半导体的表面的方法。在衬底上形成第一半导体层，并且在第一半导体层上形成第二半导体层。随后，在第二半导体层上形成第三半导体层，并且在第三半导体层上形成含半导体的种子。将种子退火以形成坚固的含半导体的表面。第一，第二和第三半导体层是公共堆叠的一部分，并且可以在电容器结构的存储节点内一起使用。本发明还包括包括粗糙表面的半导体结构。坚固的表面可以是例如坚固的硅。

9. 发明申请

US20060198955A1 Microfeature workpiece processing apparatus and methods for batch deposition of materials on microfeature workpieces 审中-公开
标题翻译：微型工件加工设备和微型工件上批量堆放材料的微型工件加工设备及方法
公开(公告)号：US20060198955A1
公开(公告)日：2006-09-07
申请号：US11416866
申请日：2006-05-03
申请人： Lingyi Zheng , Trung Doan , Lyle Breiner , Er-Xuan Ping , Ronald Weimer , David Kubista , Kevin Beaman , Cem Basceri
发明人： Lingyi Zheng , Trung Doan , Lyle Breiner , Er-Xuan Ping , Ronald Weimer , David Kubista , Kevin Beaman , Cem Basceri
IPC分类号： C23C16/00
CPC分类号： C23C16/4583 , C23C16/45546 , C23C16/45578 , Y10S206/832
摘要： The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor using atomic layer deposition. Some of these apparatus include microfeature workpiece holders that include gas distributors. One exemplary implementation provides a microfeature workpiece holder adapted to hold a plurality of microfeature workpieces. This workpiece holder includes a plurality of workpiece supports and a gas distributor. The workpiece supports are adapted to support a plurality of microfeature workpieces in a spaced-apart relationship to define a process space adjacent a surface of each microfeature workpiece. The gas distributor includes an inlet and a plurality of outlets, with each of the outlets positioned to direct a flow of process gas into one of the process spaces.
摘要翻译：本公开描述了用于处理微特征工件的装置和方法，例如通过使用原子层沉积在微电子半导体上沉积材料。这些设备中的一些包括微型工件保持器，其包括气体分配器。一个示例性实施例提供了适于保持多个微特征工件的微特征工件保持器。该工件保持器包括多个工件支撑件和气体分配器。工件支撑件适于以间隔的关系支撑多个微特征工件以限定与每个微特征工件的表面相邻的工艺空间。气体分配器包括入口和多个出口，其中每个出口被定位成将处理气体流引导到处理空间中的一个中。

10. 发明申请

US20050081786A1 Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers 失效
标题翻译：用于在反应室中将材料沉积到工件上的系统以及用于从反应室除去副产物的方法
公开(公告)号：US20050081786A1
公开(公告)日：2005-04-21
申请号：US10687458
申请日：2003-10-15
申请人： David Kubista , Trung Doan , Lyle Breiner , Ronald Weimer , Kevin Beaman , Er-Xuan Ping , Lingyi Zheng , Cem Basceri
发明人： David Kubista , Trung Doan , Lyle Breiner , Ronald Weimer , Kevin Beaman , Er-Xuan Ping , Lingyi Zheng , Cem Basceri
IPC分类号： C23C16/44 , C23C16/455 , C23C16/00
CPC分类号： C23C16/45544 , C23C16/4412 , Y10T137/0396
摘要： Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers are disclosed herein. In one embodiment, the system includes a gas phase reaction chamber, a first exhaust line coupled to the reaction chamber, first and second traps each in fluid communication with the first exhaust line, and a vacuum pump coupled to the first exhaust line to remove gases from the reaction chamber. The first and second traps are operable independently to individually and/or jointly collect byproducts from the reaction chamber. It is emphasized that this Abstract is provided to comply with the rules requiring an abstract. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：用于在反应室中将材料沉积到工件上的系统以及用于从反应室除去副产物的方法在此公开。在一个实施例中，系统包括气相反应室，连接到反应室的第一排气管线，与第一排气管线流体连通的第一和第二阱，以及耦合到第一排气管线以除去气体的真空泵从反应室。第一和第二捕集器独立地可操作地单独地和/或共同地从反应室收集副产物。要强调的是提供本摘要以符合要求摘要的规则。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式