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1. 发明授权

US07572354B2 Electrochemical processing of conductive surface 有权
标题翻译：导电表面的电化学处理
公开(公告)号：US07572354B2
公开(公告)日：2009-08-11
申请号：US11445594
申请日：2006-06-01
申请人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol , Douglas W. Young
发明人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol , Douglas W. Young
IPC分类号： C25B9/00 , C25D7/00
CPC分类号： B24B37/20 , B24B37/046 , B24B37/24 , B24B37/26 , C25D5/06 , C25D17/001 , C25D17/14 , C25F7/00 , H01L21/2885 , H01L21/76877
摘要： The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece. Upon application of power to the anode plate and the cathode workpiece, the electrolyte solution disposed in the plating apparatus is used to deposit the conductive material on the workpiece surface using cylindrical rollers having the pad or blade type objects.
摘要翻译：本发明涉及通过旋转靠近基板的垫片或刀片型物体来在半导体衬底上镀覆导电材料的方法和装置，从而消除/减少凹陷和空隙。这通过提供安装在圆柱形阳极或辊子上的垫片或刀片型物体，并使用设置在垫片上或穿过垫片上的电解质溶液将导电材料施加到衬底来实现。在本发明的一个实施例中，衬垫或刀片型物体安装在圆柱形阳极上并围绕第一轴线旋转，同时工件可以是静止的或围绕第二轴线旋转，并且来自电解质溶液的金属沉积在工件上，在工件和阳极之间施加电位差。在本发明的另一实施例中，电镀装置包括与阴极工件间隔开的阳极板。在向阳极板和阴极工件施加电力时，使用设置在电镀装置中的电解液将导电材料沉积在工件表面上，使用具有焊盘或刀片型物体的圆柱形辊。

2. 发明授权

US06630059B1 Workpeice proximity plating apparatus 失效
标题翻译：工件接近电镀设备
公开(公告)号：US06630059B1
公开(公告)日：2003-10-07
申请号：US09483095
申请日：2000-01-14
申请人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol , Douglas W. Young
发明人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol , Douglas W. Young
IPC分类号： C25D1700
CPC分类号： B24B37/20 , B24B37/046 , B24B37/24 , B24B37/26 , C25D5/06 , C25D17/001 , C25D17/14 , C25F7/00 , H01L21/2885 , H01L21/76877
摘要： The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece. Upon application of power to the anode plate and the cathode workpiece, the electrolyte solution disposed in the plating apparatus is used to deposit the conductive material on the workpiece surface using cylindrical rollers having the pad or blade type objects.
摘要翻译：本发明涉及通过旋转靠近基板的垫片或刀片型物体来在半导体衬底上镀覆导电材料的方法和装置，从而消除/减少凹陷和空隙。这通过提供安装在圆柱形阳极或辊子上的垫片或刀片型物体，并使用设置在垫片上或穿过垫片上的电解质溶液将导电材料施加到衬底来实现。在本发明的一个实施例中，衬垫或刀片型物体安装在圆柱形阳极上并围绕第一轴线旋转，同时工件可以是静止的或围绕第二轴线旋转，并且来自电解质溶液的金属沉积在工件上，在工件和阳极之间施加电位差。在本发明的另一实施例中，电镀装置包括与阴极工件间隔开的阳极板。在向阳极板和阴极工件施加电力时，使用设置在电镀装置中的电解液将导电材料沉积在工件表面上，使用具有焊盘或刀片型物体的圆柱形辊。

3. 发明授权

US06666959B2 Semiconductor workpiece proximity plating methods and apparatus 有权
标题翻译：半导体工件接近电镀方法和装置
公开(公告)号：US06666959B2
公开(公告)日：2003-12-23
申请号：US09976972
申请日：2001-10-11
申请人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol , Douglas W. Young
发明人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol , Douglas W. Young
IPC分类号： C25D1700
CPC分类号： B24B37/20 , B24B37/046 , B24B37/24 , B24B37/26 , C25D5/06 , C25D17/001 , C25D17/14 , C25F7/00 , H01L21/2885 , H01L21/76877
摘要： The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece. Upon application of power to the anode plate and the cathode workpiece, the electrolyte solution disposed in the plating apparatus is used to deposit the conductive material on the workpiece surface using cylindrical rollers having the pad or blade type objects.
摘要翻译：本发明涉及通过旋转靠近基板的垫片或刀片型物体来在半导体衬底上镀覆导电材料的方法和装置，从而消除/减少凹陷和空隙。这通过提供安装在圆柱形阳极或辊子上的垫片或刀片型物体，并使用设置在垫片上或穿过垫片上的电解质溶液将导电材料施加到衬底来实现。在本发明的一个实施例中，衬垫或刀片型物体安装在圆柱形阳极上并围绕第一轴线旋转，同时工件可以是静止的或围绕第二轴线旋转，并且来自电解质溶液的金属沉积在工件上，在工件和阳极之间施加电位差。在本发明的另一实施例中，电镀装置包括与阴极工件间隔开的阳极板。在向阳极板和阴极工件施加电力时，使用设置在电镀装置中的电解液将导电材料沉积在工件表面上，使用具有焊盘或刀片型物体的圆柱形辊。

4. 发明授权

US06905588B2 Packaging deposition methods 失效
标题翻译：包装沉积方法
公开(公告)号：US06905588B2
公开(公告)日：2005-06-14
申请号：US09905335
申请日：2001-07-13
申请人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
发明人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
IPC分类号： C25D3/02 , C23C28/00 , C25D5/10 , C25D7/12 , H01L21/288 , H01L21/304 , H01L21/60 , H01L21/768 , C25D5/00 , B23H3/00
CPC分类号： C25D5/00 , C23C18/1608 , C23C18/165 , C23C18/1651 , C23C18/1653 , C23C18/1696 , C23C18/1848 , C23C18/31 , C25D5/02 , C25D5/10 , C25D5/22 , C25D5/34 , H01L21/2885 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76865 , H01L21/76871 , H01L21/76874 , H01L21/76876 , H01L21/76879 , H01L21/76885 , H01L24/11 , H01L2221/1089 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01016 , H01L2924/01019 , H01L2924/01021 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01057 , H01L2924/0106 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/3011
摘要： The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
摘要翻译：本发明涉及一种制造高性能芯片互连和封装的方法，该方法通过提供以更高效和省时的方式在衬底的空腔中沉积导电材料的方法。这是通过从衬底的顶表面选择性地去除种子层的部分，然后在衬底的空腔中沉积导电材料，其中种子层的部分保留在空腔中。另一种方法包括在衬底的顶表面上形成氧化物层，使得导电材料可以沉积在空腔中，而不会在衬底的顶表面上形成材料。本发明还公开了用于形成多级互连的方法和相应的结构。

5. 发明授权

US06355153B1 Chip interconnect and packaging deposition methods and structures 有权
标题翻译：芯片互连和封装沉积方法和结构
公开(公告)号：US06355153B1
公开(公告)日：2002-03-12
申请号：US09398258
申请日：1999-09-17
申请人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
发明人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
IPC分类号： C25D500
CPC分类号： C25D5/00 , C23C18/1608 , C23C18/165 , C23C18/1651 , C23C18/1653 , C23C18/1696 , C23C18/1848 , C23C18/31 , C25D5/02 , C25D5/10 , C25D5/22 , C25D5/34 , H01L21/2885 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76865 , H01L21/76871 , H01L21/76874 , H01L21/76876 , H01L21/76879 , H01L21/76885 , H01L24/11 , H01L2221/1089 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01016 , H01L2924/01019 , H01L2924/01021 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01057 , H01L2924/0106 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/3011
摘要： The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
摘要翻译：本发明涉及一种制造高性能芯片互连和封装的方法，该方法通过提供以更高效和省时的方式在衬底的空腔中沉积导电材料的方法。这是通过从衬底的顶表面选择性地去除种子层的部分，然后在衬底的空腔中沉积导电材料，其中种子层的部分保留在空腔中。另一种方法包括在衬底的顶表面上形成氧化物层，使得导电材料可以沉积在空腔中，而不会在衬底的顶表面上形成材料。本发明还公开了用于形成多级互连的方法和相应的结构。

6. 发明授权

US07147766B2 Chip interconnect and packaging deposition methods and structures 有权
公开(公告)号：US07147766B2
公开(公告)日：2006-12-12
申请号：US10407892
申请日：2003-04-04
申请人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
发明人： Cyprian Emeka Uzoh , Homayoun Talieh , Bulent Basol
IPC分类号： C25D5/02 , C25D5/48 , C25D5/52
CPC分类号： C25D5/00 , C23C18/1608 , C23C18/165 , C23C18/1651 , C23C18/1653 , C23C18/1696 , C23C18/1848 , C23C18/31 , C25D5/02 , C25D5/10 , C25D5/22 , C25D5/34 , H01L21/2885 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76865 , H01L21/76871 , H01L21/76874 , H01L21/76876 , H01L21/76879 , H01L21/76885 , H01L24/11 , H01L2221/1089 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01016 , H01L2924/01019 , H01L2924/01021 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01057 , H01L2924/0106 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/3011
摘要： The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

7. 发明申请

US20060219573A1 Apparatus with conductive pad for electroprocessing 有权
标题翻译：具有电加工导电垫的装置
公开(公告)号：US20060219573A1
公开(公告)日：2006-10-05
申请号：US11445594
申请日：2006-06-01
申请人： Cyprian Uzoh , Homayoun Talieh , Bulent Basol , Douglas Young
发明人： Cyprian Uzoh , Homayoun Talieh , Bulent Basol , Douglas Young
IPC分类号： B23H3/00
CPC分类号： B24B37/20 , B24B37/046 , B24B37/24 , B24B37/26 , C25D5/06 , C25D17/001 , C25D17/14 , C25F7/00 , H01L21/2885 , H01L21/76877
摘要： The present invention relates to methods and apparatus for plating a conductive material on a semiconductor substrate by rotating pad or blade type objects in close proximity to the substrate, thereby eliminating/reducing dishing and voids. This is achieved by providing pad or blade type objects mounted on cylindrical anodes or rollers and applying the conductive material to the substrate using the electrolyte solution disposed on or through the pads, or on the blades. In one embodiment of the invention, the pad or blade type objects are mounted on the cylindrical anodes and rotated about a first axis while the workpiece may be stationary or rotate about a second axis, and metal from the electrolyte solution is deposited on the workpiece when a potential difference is applied between the workpiece and the anode. In another embodiment of the present invention, the plating apparatus includes an anode plate spaced apart from the cathode workpiece. Upon application of power to the anode plate and the cathode workpiece, the electrolyte solution disposed in the plating apparatus is used to deposit the conductive material on the workpiece surface using cylindrical rollers having the pad or blade type objects.
摘要翻译：本发明涉及通过旋转靠近基板的垫片或刀片型物体来在半导体衬底上镀覆导电材料的方法和装置，从而消除/减少凹陷和空隙。这通过提供安装在圆柱形阳极或辊子上的垫片或刀片型物体，并使用设置在垫片上或穿过垫片上的电解质溶液将导电材料施加到衬底来实现。在本发明的一个实施例中，衬垫或刀片型物体安装在圆柱形阳极上并围绕第一轴线旋转，同时工件可以是静止的或围绕第二轴线旋转，并且来自电解质溶液的金属沉积在工件上，在工件和阳极之间施加电位差。在本发明的另一实施例中，电镀装置包括与阴极工件间隔开的阳极板。在向阳极板和阴极工件施加电力时，使用设置在电镀装置中的电解液将导电材料沉积在工件表面上，使用具有焊盘或刀片型物体的圆柱形辊。

8. 发明申请

US20060070885A1 Chip interconnect and packaging deposition methods and structures 审中-公开
公开(公告)号：US20060070885A1
公开(公告)日：2006-04-06
申请号：US11295014
申请日：2005-12-06
申请人： Cyprian Uzoh , Homayoun Talieh , Bulent Basol
发明人： Cyprian Uzoh , Homayoun Talieh , Bulent Basol
IPC分类号： C25D5/02 , C25D5/48
CPC分类号： C25D5/00 , C23C18/1608 , C23C18/165 , C23C18/1651 , C23C18/1653 , C23C18/1696 , C23C18/1848 , C23C18/31 , C25D5/02 , C25D5/10 , C25D5/22 , C25D5/34 , H01L21/2885 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76865 , H01L21/76871 , H01L21/76874 , H01L21/76876 , H01L21/76879 , H01L21/76885 , H01L24/11 , H01L2221/1089 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01016 , H01L2924/01019 , H01L2924/01021 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01057 , H01L2924/0106 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/3011
摘要： The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

9. 发明申请

US20060042934A1 Method and apparatus for forming an electrical contact with a semiconductor substrate 有权
公开(公告)号：US20060042934A1
公开(公告)日：2006-03-02
申请号：US11259694
申请日：2005-10-25
申请人： Homayoun Talieh , Bulent Basol
发明人： Homayoun Talieh , Bulent Basol
IPC分类号： C25D17/00
CPC分类号： H01L21/6715 , C25D17/001 , H01L21/2885 , H01L21/67075
摘要： The present invention is directed to a method and apparatus for plating a surface of a semiconductor workpiece (wafer, flat panel, magnetic films, etc.) using a liquid conductor that makes contact with the outer surface of the workpiece. The liquid conductor is stored in a reservoir and pump through an inlet channel to the liquid chamber. The liquid conductor is injected into a liquid chamber such that the liquid conductor makes contact with the outer surface of the workpiece. An inflatable tube is also provided to prevent the liquid conductor from reaching the back face of the workpiece. A plating solution can be applied to the front face of the workpiece where a retaining ring/seal further prevents the plating solution and the liquid conductor from making contact with each other. In an alternative embodiment, electrical contacts may be formed using an inflatable tube that has either been coated with a conductive material or contains a conductive object. The inflatable tube further provides uniform contact and pressure along the periphery of the workpiece, which may not necessarily be perfectly flat, because the tube can conform according to the shape of the periphery of the workpiece. Further, the present invention can be used to dissolve/etch a metal layer from the periphery of the workpiece.

10. 发明授权

US06974769B2 Conductive structure fabrication process using novel layered structure and conductive structure fabricated thereby for use in multi-level metallization 失效
标题翻译：导电结构制造工艺使用新颖的层状结构和导电结构，由此制成，用于多层次金属化
公开(公告)号：US06974769B2
公开(公告)日：2005-12-13
申请号：US10663318
申请日：2003-09-16
申请人： Bulent Basol , Homayoun Talieh , Cyprian Uzoh
发明人： Bulent Basol , Homayoun Talieh , Cyprian Uzoh
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/7684
摘要： Conductive structures in features of an insulator layer on a substrate are fabricated by a particular process. In this process, a layer of conductive material is applied over the insulator layer so that the layer of conductive material covers field regions adjacent the features and fills in the features themselves. A grain size differential between the conductive material which covers the field regions and the conductive material which fills in the features is then established by annealing the layer of conductive material. Excess conductive material is then removed to uncover the field regions and leave the conductive structures. The layer of conductive material is applied so as to define a first layer thickness over the field regions and a second layer thickness in and over the features. These thicknesses are dimensioned such that d1≦0.5d2, with d1 being the first layer thickness and d2 being the second layer thickness. Preferably, the first and second layer thicknesses are dimensioned such that d1≦0.3d2.
摘要翻译：通过特定的工艺制造衬底上的绝缘体层的特征的导电结构。在该过程中，将导电材料层施加在绝缘体层上，使得导电材料层覆盖与特征相邻的场区域并填充特征本身。然后通过退火导电材料层来建立覆盖场区的导电材料与填充特征的导电材料之间的晶粒尺寸差。然后去除过量的导电材料以露出场区并留下导电结构。施加导电材料层以在场区域上限定第一层厚度，并且在特征中和之上限定第二层厚度。这些厚度的尺寸使得其中d 1是第一层厚度，d 2 <2 < / SUB>为第二层厚度。优选地，第一层厚度和第二层厚度的尺寸被确定为使得d 1 = 0.3D 2。

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