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1. 发明授权

US07750374B2 Process for forming an electronic device including a transistor having a metal gate electrode 失效
标题翻译：用于形成包括具有金属栅电极的晶体管的电子器件的工艺
公开(公告)号：US07750374B2
公开(公告)日：2010-07-06
申请号：US11559633
申请日：2006-11-14
申请人： Cristiano Capasso , Srikanth B. Samavedam , Eric J. Verret
发明人： Cristiano Capasso , Srikanth B. Samavedam , Eric J. Verret
IPC分类号： H01L29/78
CPC分类号： H01L21/823842 , H01L21/823807 , H01L29/1054
摘要： An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region including a semiconductor layer immediately adjacent to a semiconductor substrate. In one embodiment, the first work function is less than the valence band of the semiconductor layer. In another embodiment, the n-channel transistor has a second gate electrode with a second work function different from the first work function and closer to a conduction band than a valence band of a second channel region. A process of forming the electronic device includes forming first and second gate electrodes having first and second work functions, respectively. First and second channel regions having a same minority carrier type are associated with the first and second gate electrodes, respectively.
摘要翻译：电子器件包括n沟道晶体管和p沟道晶体管。 p沟道晶体管具有第一功函数的第一栅电极和包括与半导体衬底紧邻的半导体层的第一沟道区。在一个实施例中，第一功函数小于半导体层的价带。在另一个实施例中，n沟道晶体管具有第二栅极，其具有与第一功函数不同的第二功函数，并且比第二沟道区的价带更接近导带。形成电子器件的工艺包括分别形成具有第一和第二功函数的第一和第二栅电极。具有相同少数载流子类型的第一和第二沟道区分别与第一和第二栅电极相关联。

2. 发明申请

US20080111155A1 ELECTRONIC DEVICE INCLUDING A TRANSISTOR HAVING A METAL GATE ELECTRODE AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 失效
标题翻译：包括具有金属栅电极的晶体管的电子器件和用于形成电子器件的工艺
公开(公告)号：US20080111155A1
公开(公告)日：2008-05-15
申请号：US11559633
申请日：2006-11-14
申请人： Cristiano Capasso , Srikanth B. Samavedam , Eric J. Verret
发明人： Cristiano Capasso , Srikanth B. Samavedam , Eric J. Verret
IPC分类号： H01L27/088 , H01L21/77
CPC分类号： H01L21/823842 , H01L21/823807 , H01L29/1054
摘要： An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region including a semiconductor layer immediately adjacent to a semiconductor substrate. In one embodiment, the first work function is less than the valence band of the semiconductor layer. In another embodiment, the n-channel transistor has a second gate electrode with a second work function different from the first work function and closer to a conduction band than a valence band of a second channel region. A process of forming the electronic device includes forming first and second gate electrodes having first and second work functions, respectively. First and second channel regions having a same minority carrier type are associated with the first and second gate electrodes, respectively.
摘要翻译：电子器件包括n沟道晶体管和p沟道晶体管。 p沟道晶体管具有第一功函数的第一栅电极和包括与半导体衬底紧邻的半导体层的第一沟道区。在一个实施例中，第一功函数小于半导体层的价带。在另一个实施例中，n沟道晶体管具有第二栅极，其具有与第一功函数不同的第二功函数，并且比第二沟道区的价带更接近导带。形成电子器件的工艺包括分别形成具有第一和第二功函数的第一和第二栅电极。具有相同少数载流子类型的第一和第二沟道区分别与第一和第二栅电极相关联。

3. 发明申请

US20090004792A1 METHOD FOR FORMING A DUAL METAL GATE STRUCTURE 有权
标题翻译：形成双金属门结构的方法
公开(公告)号：US20090004792A1
公开(公告)日：2009-01-01
申请号：US11771721
申请日：2007-06-29
申请人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, JR.
发明人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, JR.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823814 , H01L21/823842
摘要： A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.
摘要翻译：一种用于形成半导体结构的方法包括在半导体层上形成沟道区层，其中半导体层包括第一和第二阱区，在沟道区上形成保护层，在第一阱上形成第一栅极电介质层在所述第一栅极电介质上形成第一金属栅极电极层，去除所述保护层，在所述沟道区域上形成第二栅极电介质层，在所述第二栅极介电层上方形成第二金属栅极电极层，栅极堆叠，其包括第一阱区域上的第一栅极电介质层和第一金属栅电极层中的每一个的一部分，并且形成包括第二栅极电介质层和第二金属栅极电极层中的每一个的第二栅极堆叠，通道区域层。

4. 发明授权

US07910442B2 Process for making a semiconductor device using partial etching 有权
标题翻译：使用局部蚀刻制造半导体器件的工艺
公开(公告)号：US07910442B2
公开(公告)日：2011-03-22
申请号：US11782319
申请日：2007-07-24
申请人： William J. Taylor, Jr. , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer
发明人： William J. Taylor, Jr. , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/84
摘要： A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.
摘要翻译：提供了一种包括部分蚀刻第一层的第一部分的方法，其中第一层是导电层。该方法还包括去除第二层的至少一部分。该方法还包括完成导电层的所述第一部分的蚀刻，使得导电层的所述第一部分被去除。该方法还包括完成半导体器件的形成。

5. 发明授权

US07666730B2 Method for forming a dual metal gate structure 有权
标题翻译：双金属栅极结构的形成方法
公开(公告)号：US07666730B2
公开(公告)日：2010-02-23
申请号：US11771721
申请日：2007-06-29
申请人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, Jr.
发明人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, Jr.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823814 , H01L21/823842
摘要： A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.
摘要翻译：一种用于形成半导体结构的方法包括在半导体层上形成沟道区层，其中半导体层包括第一和第二阱区，在沟道区上形成保护层，在第一阱上形成第一栅极电介质层在所述第一栅极电介质上形成第一金属栅极电极层，去除所述保护层，在所述沟道区域上形成第二栅极电介质层，在所述第二栅极介电层上方形成第二金属栅极电极层，栅极堆叠，其包括第一阱区域上的第一栅极电介质层和第一金属栅电极层中的每一个的一部分，并且形成包括第二栅极电介质层和第二金属栅极电极层中的每一个的第二栅极堆叠，通道区域层。

6. 发明申请

US20090029538A1 PROCESS FOR MAKING A SEMICONDUCTOR DEVICE USING PARTIAL ETCHING 有权
标题翻译：使用部分蚀刻制造半导体器件的工艺
公开(公告)号：US20090029538A1
公开(公告)日：2009-01-29
申请号：US11782319
申请日：2007-07-24
申请人： William J. Taylor, JR. , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer
发明人： William J. Taylor, JR. , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer
IPC分类号： H01L21/302 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/82345 , H01L21/84
摘要： A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device.
摘要翻译：提供了一种包括部分蚀刻第一层的第一部分的方法，其中第一层是导电层。该方法还包括去除第二层的至少一部分。该方法还包括完成导电层的所述第一部分的蚀刻，使得导电层的所述第一部分被去除。该方法还包括完成半导体器件的形成。

7. 发明授权

US07445981B1 Method for forming a dual metal gate structure 有权
标题翻译：双金属栅极结构的形成方法
公开(公告)号：US07445981B1
公开(公告)日：2008-11-04
申请号：US11771690
申请日：2007-06-29
申请人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, Jr.
发明人： Gauri V. Karve , Cristiano Capasso , Srikanth B. Samavedam , James K. Schaeffer , William J. Taylor, Jr.
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/823857
摘要： A method includes forming a first gate dielectric layer over a semiconductor layer having a first and a second well region, forming a first metal gate electrode layer over the first gate dielectric, forming a sidewall protection layer over the first metal gate electrode layer and adjacent sidewalls of the first gate dielectric layer and first metal gate electrode layer, forming a channel region layer over the second well region, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and second metal gate electrode layer over the channel region layer and over the second well region.
摘要翻译：一种方法包括在具有第一和第二阱区的半导体层上形成第一栅极电介质层，在第一栅极电介质上方形成第一金属栅电极层，在第一金属栅电极层和相邻侧壁上形成侧壁保护层的第一栅介质层和第一金属栅极电极层，在第二阱区上形成沟道区，在沟道区上形成第二栅介质层，形成第二栅极电极层，形成第一栅叠层包括第一阱区域上的第一栅极电介质层和第一金属栅极电极层中的每一个的一部分，并且形成第二栅极堆叠，其包括沟道区域上的第二栅极介电层和第二金属栅极电极层中的每一个的第二栅极堆叠并在第二个井区域。

8. 发明申请

US20130249015A1 SEMICONDUCTOR DEVICES WITH DIFFERENT DIELECTRIC THICKNESSES 有权
公开(公告)号：US20130249015A1
公开(公告)日：2013-09-26
申请号：US13893026
申请日：2013-05-13
申请人： Gauri V. Karve , Mark D. Hall , Srikanth B. Samavedam
发明人： Gauri V. Karve , Mark D. Hall , Srikanth B. Samavedam
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.

9. 发明授权

US08178401B2 Method for fabricating dual-metal gate device 有权
标题翻译：双金属栅极器件制造方法
公开(公告)号：US08178401B2
公开(公告)日：2012-05-15
申请号：US11530058
申请日：2006-09-08
申请人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
发明人： David C. Gilmer , Srikanth B. Samavedam , Philip J. Tobin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.
摘要翻译：一种制造包括由异型金属形成的双金属栅极的MOS晶体管的方法。诸如HfO 2的栅极电介质（34）沉积在半导体衬底上。牺牲层（35）接着沉积在栅极电介质上。牺牲层被图案化，使得衬底的第一（pMOS，例如）区域（32）上的栅极电介质被暴露，并且衬底的第二（nMOS，例如）区域（33）上的栅极电介质继续是受牺牲层保护。第一栅极导体材料（51）沉积在剩余的牺牲区域上并暴露在栅极电介质上。图案化第一栅极导体材料，使得衬底的第二区域上方的第一栅极导体材料被蚀刻掉。第二区域上的牺牲层防止在去除第一栅极导体材料时损坏下面的介电材料。

10. 发明申请

US20090108296A1 SEMICONDUCTOR DEVICES WITH DIFFERENT DIELECTRIC THICKNESSES 有权
标题翻译：具有不同介质厚度的半导体器件
公开(公告)号：US20090108296A1
公开(公告)日：2009-04-30
申请号：US11931565
申请日：2007-10-31
申请人： Gauri V. Karve , Mark D. Hall , Srikanth B. Samavedam
发明人： Gauri V. Karve , Mark D. Hall , Srikanth B. Samavedam
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823857 , H01L29/1054
摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
摘要翻译：具有具有不同厚度的电介质层的器件的集成电路。电介质层包括高k电介质，并且一些电介质层包括由氧化工艺形成的氧化物层。每个器件包括位于器件的电极堆叠下方的包含锗或碳的层。硅层位于包含锗或碳的层之上。

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