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1. 发明申请

WO2006057686A3 CAP LAYERS AND/OR PASSIVATION LAYERS FOR NITRIDE-BASED TRANSISTORS, TRANSISTOR STRUCTURES AND METHODS OF FABRICATING SAME 审中-公开
公开(公告)号：WO2006057686A3
公开(公告)日：2006-06-01
申请号：PCT/US2005/031272
申请日：2005-08-31
申请人： CREE, INC. , SAXLER, Adam, William , SHEPPARD, Scott , SMITH, Richard, Peter
发明人： SAXLER, Adam, William , SHEPPARD, Scott , SMITH, Richard, Peter
IPC分类号： H01L29/778 , H01L21/335 , H01L21/318
摘要： High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include a cap layer having a doped region adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. Graphitic BN passivation structures for wide bandgap semiconductor devices are provided. SiC passivation structures for Group III-nitride semiconductor devices are provided. Oxygen anneals of passivation structures are also provided. Ohmic contacts without a recess are also provided.

2. 发明申请

WO2005074013A2 SILICON CARBIDE ON DIAMOND SUBSTRATES AND RELATED DEVICES AND METHODS 审中-公开
标题翻译：碳化硅在金刚石基板上的相关装置和方法
公开(公告)号：WO2005074013A2
公开(公告)日：2005-08-11
申请号：PCT/US2005/002221
申请日：2005-01-14
申请人： CREE, INC. , SAXLER, Adam, William
发明人： SAXLER, Adam, William
IPC分类号： H01L21/00
CPC分类号： H01L29/1602 , H01L21/02378 , H01L21/02527 , H01L21/0254 , H01L29/778
摘要： A method of forming a high-power, high-frequency device in wide bandgap semiconductor materials with reduced junction temperature, higher power density during operation and improved reliability at a rated power density is disclosed, along with resulting semiconductor structures and devices. The method includes adding a layer of diamond to a silicon carbide wafer to increase the thermal conductivity of the resulting composite wafer, thereafter reducing the thickness of the silicon carbide portion of the composite wafer while retaining sufficient thickness of silicon carbide to support epitaxial growth thereon, preparing the silicon carbide surface of the composite wafer for epitaxial growth thereon, and adding a Group III nitride heterostructure to the prepared silicon carbide face of the wafer.
摘要翻译：公开了一种在宽带隙半导体材料中形成具有降低的结温，功率密度更高的功率密度以及额定功率密度下的可靠性提高的高功率高频器件的方法，半导体结构和器件。该方法包括向碳化硅晶片添加金刚石层以增加所得复合晶片的热导率，之后减小复合晶片的碳化硅部分的厚度同时保持足够厚度的碳化硅以支持其上的外延生长，准备用于在其上外延生长的复合晶片的碳化硅表面，并向所制备的晶片的碳化硅面添加III族氮化物异质结构。

3. 发明申请

WO2006022872A1 NITRIDE-BASED TRANSISTORS HAVING LATERALLY GROWN ACTIVE REGION AND METHODS OF FABRICATING SAME 审中-公开
标题翻译：具有横向生长活性区域的氮化物晶体管及其制造方法
公开(公告)号：WO2006022872A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/010869
申请日：2005-03-30
申请人： CREE, INC. , SAXLER, Adam, William , SHEPPARD, Scott, T. , SMITH, Richard, Peter
发明人： SAXLER, Adam, William , SHEPPARD, Scott, T. , SMITH, Richard, Peter
IPC分类号： H01L29/778 , H01L21/335 , H01L21/20
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/66462
摘要： High electron mobility transistors and/or methods of fabricating high electron mobility transistors that include a first Group III-nitride layer having vertically grown regions, laterally grown regions and a coalescence region are provided. A Group III-nitride channel layer is provided on the first Group III-nitride layer and a Group III-nitride barrier layer is provided on the Group III-nitride channel layer. A drain contact, a source contact and a gate contact are provided on the barrier layer. The gate contact is disposed on a portion of the barrier layer on a laterally grown region of the first Group III-nitride layer and at least a portion of one of the source contact and/or the drain contact is disposed on a portion of the barrier layer on a vertically grown region of the first Group III-nitride layer.
摘要翻译：提供了高电子迁移率晶体管和/或制造高电子迁移率晶体管的方法，其包括具有垂直生长区域，横向生长区域和聚结区域的第一III族氮化物层。 III族氮化物沟道层设置在第一III族氮化物层上，III族氮化物阻挡层设置在III族氮化物沟道层上。漏极接触，源极接触和栅极接触设置在阻挡层上。栅极触点设置在第一III族氮化物层的横向生长区域上的阻挡层的一部分上，并且源极接触和/或漏极接触中的一个的至少一部分设置在屏障的一部分上在第一III族氮化物层的垂直生长区上。

4. 发明申请

WO2004008495A2 NITRIDE-BASED TRANSISTORS AND METHODS OF FABRICATION THEREOF USING NON-ETCHED CONTACT RECESSES 审中-公开
标题翻译：基于氮化物的晶体管及其使用非蚀刻接触继电器的制造方法
公开(公告)号：WO2004008495A2
公开(公告)日：2004-01-22
申请号：PCT/US2003/021895
申请日：2003-07-15
申请人： CREE, INC. , SAXLER, Adam, William , SMITH, Richard, Peter , SHEPPARD, Scott, T.
发明人： SAXLER, Adam, William , SMITH, Richard, Peter , SHEPPARD, Scott, T.
IPC分类号： H01L
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/7787
摘要： Contacts for a nitride based transistor and methods of fabricating such contacts provide a recess through a regrowth process. The contacts are formed in the recess. The regrowth process includes fabricating a first cap layer comprising a Group III-nitride semiconductor material. A mask is fabricated and patterned on the first cap layer. The pattern of the mask corresponds to the pattern of the recesses for the contacts. A second cap layer comprising a Group III-nitride semiconductor material is selectively fabricated (e.g. grown) on the first cap layer utilizing the patterned mask. Additional layers may also be formed on the second cap layer. The mask may be removed to provide recess(es) to the first cap layer, and contact(s) may be formed in the recess(es). Alternatively, the mask may comprise a conductive material upon which a contact may be formed, and may not require removal.
摘要翻译：用于氮化物基晶体管的触点和制造这种触点的方法通过再生长工艺提供凹陷。触点形成在凹部中。再生过程包括制造包含III族氮化物半导体材料的第一盖层。在第一盖层上制造和图案化掩模。掩模的图案对应于用于触点的凹部的图案。使用图案化掩模，在第一盖层上选择性地制造（例如，生长）包含III族氮化物半导体材料的第二盖层。另外的层也可以形成在第二盖层上。可以去除掩模以将凹部提供给第一盖层，并且接触可以形成在凹部中。或者，掩模可以包括导电材料，可以在其上形成接触，并且可以不需要去除。

5. 发明申请

WO2007005074A1 GROUP III NITRIDE LAYERS ON SILICON CARBIDE SUBSTRATES 审中-公开
标题翻译：第三组氮化硅衬底上的碳化硅衬底
公开(公告)号：WO2007005074A1
公开(公告)日：2007-01-11
申请号：PCT/US2006/010482
申请日：2006-03-20
申请人： CREE, INC. , SAXLER, Adam, William
发明人： SAXLER, Adam, William
IPC分类号： H01L29/778
CPC分类号： H01L29/7787 , H01L29/1608 , H01L29/2003
摘要： Group III nitride semiconductor device structures are provided that include a silicon carbide (SiC) substrate and a Group III nitride epitaxial layer above the SiC substrate. The Group III nitride epitaxial layer has a dislocation density of less than about 4x10 8 cm -2 and/or an isolation voltage of at least about 50V.
摘要翻译：提供了在SiC衬底之上包括碳化硅（SiC）衬底和III族氮化物外延层的III族氮化物半导体器件结构。 III族氮化物外延层的位错密度小于约4×10 8 cm -2和/或至少约50V的隔离电压。

6. 发明申请

WO2006135477A1 GROUP III NITRIDE EPITAXIAL LAYERS ON SILICON CARBIDE SUBSTRATES 审中-公开
标题翻译：碳化硅基体上的III类氮化物外延层
公开(公告)号：WO2006135477A1
公开(公告)日：2006-12-21
申请号：PCT/US2006/012930
申请日：2006-04-05
申请人： CREE, INC. , SAXLER, Adam, William , HUTCHINS, Edward, Lloyd
发明人： SAXLER, Adam, William , HUTCHINS, Edward, Lloyd
IPC分类号： H01L29/778
CPC分类号： C30B29/36 , C30B29/403 , C30B29/406 , H01L29/2003 , H01L29/7787
摘要： A semiconductor structure is disclosed that includes a silicon carbide wafer having a diameter of at least 100 mm with a Group III nitride heterostructure on the wafer that exhibits high uniformity in a number of characteristics. These include: a standard deviation in sheet resistivity across the wafer less than three percent; a standard deviation in electron mobility across the wafer of less than 1 percent; a standard deviation in carrier density across the wafer of no more than about 3.3 percent; and a standard deviation in conductivity across the wafer of about 2.5 percent.
摘要翻译：公开了一种半导体结构，其包括具有至少100mm直径的碳化硅晶片，晶片上的III族氮化物异质结构在许多特性方面表现出高均匀性。这些包括：晶片上电阻率的标准偏差小于3％; 晶片上电子迁移率的标准偏差小于1％; 晶圆上载流子密度的标准偏差不超过约3.3％; 并且晶片上的电导率的标准偏差约为2.5％。

7. 发明申请

WO2006101598A3 GROUP III NITRIDE FIELD EFFECT TRANSISTORS 审中-公开
公开(公告)号：WO2006101598A3
公开(公告)日：2006-09-28
申请号：PCT/US2006/003259
申请日：2006-01-30
申请人： CREE, INC. , SMITH, Richard, Peter , SHEPPARD, Scott, T. , SAXLER, Adam, William , WU, Yifeng
发明人： SMITH, Richard, Peter , SHEPPARD, Scott, T. , SAXLER, Adam, William , WU, Yifeng
IPC分类号： H01L29/778 , H01L29/20 , H01L29/207 , H01L29/423
摘要： Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (V DS ) of about 56 volts, a gate to source voltage (V gs ) of from about -8 to about -14 volts and a temperature of about 140 °C for at least about 10 hours.

8. 发明申请

WO2004025719A2 NITROGEN PASSIVATION OF INTERFACE STATES IN SIO2/SIC STRUCTURES 审中-公开
标题翻译： SIO2 / SIC结构中氮界面钝化的界面态
公开(公告)号：WO2004025719A2
公开(公告)日：2004-03-25
申请号：PCT/US2003/026605
申请日：2003-08-25
申请人： CREE, INC. , SAXLER, Adam, William , DAS, Mrinal, Kanti
发明人： SAXLER, Adam, William , DAS, Mrinal, Kanti
IPC分类号： H01L21/314
CPC分类号： H01L21/049 , H01L21/3143 , H01L21/3145
摘要： A nitrided oxide layer on a silicon carbide layer is processed by annealing the nitrided oxide layer in a substantially oxygen-free nitrogen containing ambient. The anneal may be carried out at a temperature of greater than about 900 °C, for example, a temperature of about 1100 °C, a temperature of about 1200 °C or a temperature of about 1300 °C. Annealing the nitrided oxide layer may be carried out at a pressure of less than about 1 atmosphere, for example, at a pressure of from about 0.01 to about 1 atm or, in particular, at a pressure of about 0.2 atm. The nitrided oxide layer may be an oxide layer that is grown in a N 2 O and/or NO containing ambient, that is annealed in a N 2 O and/or NO containing ambient or that is grown and annealed in a N 2 O and/or NO containing ambient.
摘要翻译：通过在基本上无氧的含氮环境中退火氮化氧化物层来处理碳化硅层上的氮化氧化物层。退火可以在大于约900℃的温度下进行，例如约1100℃的温度，约1200℃的温度或约1300℃的温度。退火氮化氧化物层可以在小于约1个大气压的压力下进行，例如在约0.01至约1atm的压力下，或者特别是在约0.2atm的压力下进行。氮化氧化物层可以是在N 2 O和/或含NO的环境中生长的氧化物层，其在N 2 O和/或NO中退火含氮的环境中，或者在N 2 O和/或含NO的环境中生长并退火。

9. 发明申请

WO2007136519A1 SEMICONDUCTOR DEVICES INCLUDING SELF ALIGNED REFRACTORY CONTACTS AND METHODS OF FABRICATING THE SAME 审中-公开
标题翻译：包括自对准耐火接头的半导体器件及其制造方法
公开(公告)号：WO2007136519A1
公开(公告)日：2007-11-29
申请号：PCT/US2007/010769
申请日：2007-05-03
申请人： CREE, INC. , SAXLER, Adam, William , SHEPPARD, Scott
发明人： SAXLER, Adam, William , SHEPPARD, Scott
IPC分类号： H01L21/335 , H01L29/778
CPC分类号： H01L29/7787 , H01L21/3245 , H01L29/2003 , H01L29/66462
摘要： Methods of forming semiconductor devices are provided by forming a semiconductor layer on a semiconductor substrate. A mask is formed on the semiconductor layer. Ions having a first conductivity type are implanted into the semiconductor layer according to the mask to form implanted regions on the semiconductor layer. Metal layers are formed on the implanted regions according to the mask. The implanted regions and the metal layers are annealed in a single step to respectively activate the implanted ions in the implanted regions and provide ohmic contacts on the implanted regions. Related devices are also provided.
摘要翻译：通过在半导体衬底上形成半导体层来提供形成半导体器件的方法。在半导体层上形成掩模。具有第一导电类型的离子根据掩模注入到半导体层中，以在半导体层上形成注入区域。根据掩模在注入区域上形成金属层。注入区域和金属层在单个步骤中退火以分别激活注入区域中的注入离子并在注入区域上提供欧姆接触。还提供了相关设备。

10. 发明申请

WO2006096249A3 HIGH ELECTRON MOBILITY TRANSISTOR 审中-公开
公开(公告)号：WO2006096249A3
公开(公告)日：2006-09-14
申请号：PCT/US2006/002330
申请日：2006-01-24
申请人： CREE, INC. , SAXLER, Adam, William
发明人： SAXLER, Adam, William
IPC分类号： H01L31/00
摘要： A HEMT device including a GaN channel structure including a very thin (Al,In,Ga)N subchannel layer (14) that is disposed between a first GaN channel layer (12) and a second GaN channel layer (16), to effect band bending induced from the piezoelectric and spontaneous charges associated with the (Al,In,Ga)N subchannel layer. This GaN channel/(Al,In,Ga)N subchannel arrangement effectively disperses the 2DEG throughout the channel of the device, thereby rendering the device more linear in character (relative to a corresponding device lacking the subchannel (Al5In3Ga)N sub-layer), without substantial loss of electron mobility.

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