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1. 发明申请

US20080256306A1 NON-INCLUSIVE CACHE SYSTEMS AND METHODS 有权
标题翻译：非包容性缓存系统和方法
公开(公告)号：US20080256306A1
公开(公告)日：2008-10-16
申请号：US11733857
申请日：2007-04-11
申请人： Craig Warner , Dan Robinson , John Wastlick , Michael Schroeder
发明人： Craig Warner , Dan Robinson , John Wastlick , Michael Schroeder
IPC分类号： G06F12/16
CPC分类号： G06F12/084 , G06F12/0831
摘要： Non-inclusive cache systems and methods are provided. In one embodiment a non-inclusive cache system is provided comprising a non-inclusive cache and a cache agent that receives a request for access to the non-inclusive cache and denies the request for access to the non-inclusive cache if the non-inclusive cache system exceeds a predetermined level of activity.
摘要翻译：提供非包容性缓存系统和方法。在一个实施例中，提供了非包容性缓存系统，其包括非包容性高速缓存和高速缓存代理，其接收对非包容性高速缓存的访问请求，并且如果非包容性高速缓存不允许，则拒绝对非包容性高速缓存的访问请求缓存系统超过预定的活动级别。

2. 发明授权

US08661208B2 Non-inclusive cache systems and methods 有权
标题翻译：非包容性缓存系统和方法
公开(公告)号：US08661208B2
公开(公告)日：2014-02-25
申请号：US11733857
申请日：2007-04-11
申请人： Craig Warner , Dan Robinson , John Wastlick , Michael Schroeder , Jeffrey Moy
发明人： Craig Warner , Dan Robinson , John Wastlick , Michael Schroeder , Jeffrey Moy
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F12/084 , G06F12/0831
摘要： Non-inclusive cache systems and methods are provided. In one embodiment a non-inclusive cache system is provided comprising a non-inclusive cache and a cache agent that receives a request for access to the non-inclusive cache and denies the request for access to the non-inclusive cache if the non-inclusive cache system exceeds a predetermined level of activity.
摘要翻译：提供非包容性缓存系统和方法。在一个实施例中，提供了非包容性缓存系统，其包括非包容性高速缓存和高速缓存代理，其接收对非包容性高速缓存的访问请求，并且如果非包容性高速缓存不允许，则拒绝对非包容性高速缓存的访问请求缓存系统超过预定的活动级别。

3. 发明申请

US20080270708A1 System and Method for Achieving Cache Coherency Within Multiprocessor Computer System 审中-公开
标题翻译：在多处理器计算机系统中实现缓存一致性的系统和方法
公开(公告)号：US20080270708A1
公开(公告)日：2008-10-30
申请号：US11741858
申请日：2007-04-30
申请人： Craig Warner , Bryan Hornung , Chris Michael Brueggen , Ryan L. Akkerman , Michael K. Dugan , Gary Gostin , Harvey Ray , Dan Robinson , Christopher Greer
发明人： Craig Warner , Bryan Hornung , Chris Michael Brueggen , Ryan L. Akkerman , Michael K. Dugan , Gary Gostin , Harvey Ray , Dan Robinson , Christopher Greer
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F12/0831 , G06F2212/1048
摘要： A system and method are disclosed for achieving cache coherency in a multiprocessor computer system having a plurality of sockets with processing devices and memory controllers and a plurality of memory blocks. In at least some embodiments, the system includes a plurality of node controllers capable of being respectively coupled to the respective sockets of the multiprocessor computer, a plurality of caching devices respectively coupled to the respective node controllers, and a fabric coupling the respective node controllers, by which cache line request signals can be communicated between the respective node controllers. Cache coherency is achieved notwithstanding the cache line request signals communicated between the respective node controllers due at least in part to communications between the node controllers and the respective caching devices to which the node controllers are coupled. In at least some embodiments, the caching devices track remote cache line ownership for processor and/or input/output hub caches.
摘要翻译：公开了一种用于在具有多个具有处理设备和存储器控制器以及多个存储器块的套接字的多处理器计算机系统中实现高速缓存一致性的系统和方法。在至少一些实施例中，系统包括能够分别耦合到多处理器计算机的相应插槽的多个节点控制器，分别耦合到相应节点控制器的多个高速缓存设备，以及耦合各个节点控制器的结构，由此可以在相应的节点控制器之间传送高速缓存行请求信号。尽管至少部分地由于节点控制器与节点控制器所耦合的相应的高速缓存设备之间的通信而在各个节点控制器之间传送高速缓存行请求信号，仍然实现了高速缓存一致性。在至少一些实施例中，缓存设备跟踪用于处理器和/或输入/输出集线器高速缓存的远程高速缓存行所有权。

4. 发明申请

US20090094418A1 SYSTEM AND METHOD FOR ACHIEVING CACHE COHERENCY WITHIN MULTIPROCESSOR COMPUTER SYSTEM 有权
标题翻译：在多处理器计算机系统中实现高速缓存的系统和方法
公开(公告)号：US20090094418A1
公开(公告)日：2009-04-09
申请号：US12244700
申请日：2008-10-02
申请人： Craig WARNER , Gary Gostin , Dan Robinson
发明人： Craig WARNER , Gary Gostin , Dan Robinson
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F12/0831 , G06F12/12 , G06F2212/1048
摘要： An embodiment of a multiprocessor computer system comprises main memory, a remote processor capable of accessing the main memory, a remote cache device operative to store accesses by said remote processor to said main memory, and a filter tag cache device associated with the main memory. The filter cache device is operative to store information relating to remote ownership of data in the main memory including ownership by the remote processor. The filter cache device is operative to selectively invalidate filter tag cache entries when space is required in the filter tag cache device for new cache entries. The remote cache device is responsive to events indicating that a cache entry has low value to the remote processor to send a hint to the filter tag cache device. The filter tag cache device is responsive to a hint in selecting a filter tag cache entry to invalidate.
摘要翻译：多处理器计算机系统的实施例包括主存储器，能够访问主存储器的远程处理器，可操作以存储所述远程处理器对所述主存储器的访问的远程高速缓存设备以及与主存储器相关联的过滤器标签高速缓存设备。过滤器高速缓存设备用于存储与主存储器中的数据的远程所有权有关的信息，包括远程处理器的所有权。过滤器高速缓存设备可操作以在过滤器标签高速缓存设备中为新的高速缓存条目需要空间时，选择性地使过滤器标签高速缓存条目无效。远程高速缓存设备响应于指示高速缓存条目对于远程处理器具有低值以向该过滤器标签高速缓存设备发送提示的事件。过滤器标签缓存设备响应于选择过滤器标签高速缓存条目以使其无效的提示。

5. 发明授权

US08539164B2 Cache coherency within multiprocessor computer system 有权
标题翻译：多处理器计算机系统中的缓存一致性
公开(公告)号：US08539164B2
公开(公告)日：2013-09-17
申请号：US12244700
申请日：2008-10-02
申请人： Craig Warner , Gary Gostin , Dan Robinson
发明人： Craig Warner , Gary Gostin , Dan Robinson
IPC分类号： G06F13/00
CPC分类号： G06F12/082 , G06F12/0831 , G06F12/12 , G06F2212/1048
摘要： An embodiment of a multiprocessor computer system comprises main memory, a remote processor capable of accessing the main memory, a remote cache device operative to store accesses by said remote processor to said main memory, and a filter tag cache device associated with the main memory. The filter cache device is operative to store information relating to remote ownership of data in the main memory including ownership by the remote processor. The filter cache device is operative to selectively invalidate filter tag cache entries when space is required in the filter tag cache device for new cache entries. The remote cache device is responsive to events indicating that a cache entry has low value to the remote processor to send a hint to the filter tag cache device. The filter tag cache device is responsive to a hint in selecting a filter tag cache entry to invalidate.
摘要翻译：多处理器计算机系统的实施例包括主存储器，能够访问主存储器的远程处理器，可操作以存储所述远程处理器对所述主存储器的访问的远程高速缓存设备以及与主存储器相关联的过滤器标签高速缓存设备。过滤器高速缓存设备用于存储与主存储器中的数据的远程所有权有关的信息，包括远程处理器的所有权。过滤器高速缓存设备可操作以在过滤器标签高速缓存设备中为新的高速缓存条目需要空间时，选择性地使过滤器标签高速缓存条目无效。远程高速缓存设备响应于指示高速缓存条目对于远程处理器具有低值以向该过滤器标签高速缓存设备发送提示的事件。过滤器标签缓存设备响应于选择过滤器标签高速缓存条目以使其无效的提示。

6. 发明申请

US20110238925A1 CACHE CONTROLLER AND METHOD OF OPERATION 审中-公开
标题翻译：缓存控制器和操作方法
公开(公告)号：US20110238925A1
公开(公告)日：2011-09-29
申请号：US13122544
申请日：2008-10-02
申请人： Dan Robinson
发明人： Dan Robinson
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F12/084 , G06F12/0855
摘要： In one embodiment, there are described a sectored cache system and method of operation. A cache data block comprises separately updatable cache sectors. A common tag block contains metadata for the cache sectors of the data block and is writable as a whole. A pending allocation table (PAT) contains data representing pending writes to the tag block. When writing changes data to the tag block, the changed data is broadcast to the PAT to update data representing other pending writes to the tag block so that when the other pending writes are written to the tag block changed data from received broadcasts is included.
摘要翻译：在一个实施例中，描述了扇区缓存系统和操作方法。缓存数据块包括单独可更新的高速缓存扇区。公共标签块包含数据块的高速缓存扇区的元数据，并且作为一个整体是可写的。挂起分配表（PAT）包含表示对标签块的挂起写入的数据。当写入将数据更改为标签块时，更改的数据被广播到PAT以更新表示对标签块的其他待定写入的数据，使得当其他待定写入被写入标签块时，包括来自接收到的广播的改变的数据。

7. 发明授权

US07856576B2 Method and system for managing memory transactions for memory repair 有权
标题翻译：用于管理内存修复的内存事务的方法和系统
公开(公告)号：US07856576B2
公开(公告)日：2010-12-21
申请号：US11789683
申请日：2007-04-25
申请人： Carson D. Henrion , Dan Robinson
发明人： Carson D. Henrion , Dan Robinson
IPC分类号： G06F11/00
CPC分类号： G06F12/0895 , G06F11/1064 , G11C29/76 , G11C29/883
摘要： In one embodiment, a controller for an associative memory having n ways contains circuitry for sending a request to search an indexed location in each of the n ways for a tag, wherein the tag and an index that is used to denote the indexed location form a memory address. The controller also contains circuitry, responsive to the request, for sending a set of n validity values, each validity value indicating, for a respective way, whether the indexed location is a valid location or a defective location. Additionally, the controller contains circuitry for receiving a hit signal that indicates whether a match to the tag was found at any of the indexed locations, wherein no hit is ever received for a defective location.
摘要翻译：在一个实施例中，用于具有n路的关联存储器的控制器包含电路，用于发送用于为标签以n个方式搜索索引位置的请求的电路，其中标签和用于表示索引位置的索引形成内存地址。控制器还包含响应于该请求的电路，用于发送一组n个有效值，每个有效值针对各自的方式指示索引位置是有效位置还是有缺陷位置。此外，控制器包含用于接收命中信号的电路，该命中信号指示在任何索引位置处是否找到与标签的匹配，其中没有为缺陷位置接收到命中。

8. 发明申请

US20080270703A1 Method and system for managing memory transactions for memory repair 有权
标题翻译：用于管理内存修复的内存事务的方法和系统
公开(公告)号：US20080270703A1
公开(公告)日：2008-10-30
申请号：US11789683
申请日：2007-04-25
申请人： Carson D. Henrion , Dan Robinson
发明人： Carson D. Henrion , Dan Robinson
IPC分类号： G06F12/08 , G06F11/16
CPC分类号： G06F12/0895 , G06F11/1064 , G11C29/76 , G11C29/883
摘要： In one embodiment, a controller for an associative memory having n ways contains circuitry for sending a request to search an indexed location in each of the n ways for a tag, wherein the tag and an index that is used to denote the indexed location form a memory address. The controller also contains circuitry, responsive to the request, for sending a set of n validity values, each validity value indicating, for a respective way, whether the indexed location is a valid location or a defective location. Additionally, the controller contains circuitry for receiving a hit signal that indicates whether a match to the tag was found at any of the indexed locations, wherein no hit is ever received for a defective location.
摘要翻译：在一个实施例中，用于具有n路的关联存储器的控制器包含电路，用于发送用于为标签以n个方式搜索索引位置的请求的电路，其中标签和用于表示索引位置的索引形成内存地址。控制器还包含响应于该请求的电路，用于发送一组n个有效值，每个有效值针对各自的方式指示索引位置是有效位置还是有缺陷位置。此外，控制器包含用于接收命中信号的电路，该命中信号指示在任何索引位置处是否找到与标签的匹配，其中没有为缺陷位置接收到命中。

9. 发明申请

US20130096021A1 RECURRENT GENE FUSIONS IN BREAST CANCER 审中-公开
标题翻译：乳腺癌中的现有基因融合
公开(公告)号：US20130096021A1
公开(公告)日：2013-04-18
申请号：US13629188
申请日：2012-09-27
申请人： Arul M. Chinnaiyan , Chandan Kumar-Sinha , Dan Robinson , Shanker Kalyana-Sundaram
发明人： Arul M. Chinnaiyan , Chandan Kumar-Sinha , Dan Robinson , Shanker Kalyana-Sundaram
IPC分类号： C12Q1/68 , C07K16/32
CPC分类号： C12Q1/6886 , C07K16/32 , C12Q2600/156 , G01N33/57415
摘要： The present disclosure relates to compositions and methods for cancer diagnosis, research and therapy, including but not limited to, cancer markers. In particular, the present disclosure relates to gene fusions as diagnostic markers and clinical targets for breast cancer.
摘要翻译：本公开涉及用于癌症诊断，研究和治疗的组合物和方法，包括但不限于癌症标志物。特别地，本公开涉及作为乳腺癌的诊断标记物和临床靶标的基因融合体。

10. 发明授权

US08216504B2 Molding apparatus 有权
公开(公告)号：US08216504B2
公开(公告)日：2012-07-10
申请号：US12400448
申请日：2009-03-09
申请人： Dan Robinson
发明人： Dan Robinson
IPC分类号： B29C45/74
CPC分类号： B29C45/2737 , B29C45/0013 , B29C45/0025 , B29C45/2806 , B29C2045/0027 , B29L2031/104 , B29L2031/108
摘要： A molding apparatus is configured with article molding regions that receive a direct flow of a molding material feed such that external flow channels are not needed. The article molding regions are formed into front sides of opposed “A” and “B” surface mold tools that, when moved into a mating relationship with one another, form closed molding cavities within which molded articles are generated from molding material feed. The article molding regions each generally have a body bounded by a perimeter that establishes an outer edge for an article molded in the one of the closed molding cavities. With at least the “A” surface mold tool, a port is coupled with the body of each article molding region to establish a direct pathway is through which the molding material feed flows to enter the article molding regions, and thus the closed molding cavity, without having to flow along the tool front sides outside of the article molding regions. A distribution channel extends to each port to deliver the molding material feed and a moveable blocking pin is provided for each port to alternately prevent the molding material feed from flowing through the respective port to reach the closed molding cavity and allow the molding material to flow through the respective port to reach the closed molding cavity.

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