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1. 发明授权

US4937791A High performance dynamic ram interface 失效
标题翻译：高性能动态RAM接口
公开(公告)号：US4937791A
公开(公告)日：1990-06-26
申请号：US201430
申请日：1988-06-02
申请人： Craig S. Steele , William C. Athas, Jr. , Charles L. Seitz
发明人： Craig S. Steele , William C. Athas, Jr. , Charles L. Seitz
IPC分类号： G06F12/02 , G11C11/408 , G11C11/4096
CPC分类号： G11C11/408 , G06F12/0215 , G11C11/4096
摘要： A method and associated apparatus for accessing a plurality of DRAMs in the static column mode by a high performance instruction processor to provide minimum wait state accessing thereby. The method comprises the steps of, having the instruction processor emit each instruction address as an address containing a bank number field, a row address field, and column address field; providing a table for storing a set of open pages being the current row address for each bank where a bank is associated with a respective one of the plurality DRAMs; for each instruction address emitted from the instruction processor, determining whether there is a match between the row address stored in the table and the row address emitted from the instruction processor employing the bank number as an index into the table of open pages; if the two addresses match, continuing the memory access to the indicated bank in a continuing static column mode; and, if the two addresses do not match, overwriting the old address for the indicated bank in the table with the new row address and continuing the memory access by beginning a new static column mode access to the indicated bank. In the preferred embodiment, the method includes, as necessary, aborting the access in progress if the two addresses do not match prior to beginning the new static column mode access to the indicated bank and advising the instruction processor that the access in progress is being aborted and being begun again.
摘要翻译：一种用于通过高性能指令处理器以静态列模式访问多个DRAM以提供最小等待状态访问的方法和相关联的装置。该方法包括以下步骤：使指令处理器将每个指令地址发送为包含存储体号字段，行地址字段和列地址字段的地址; 提供用于存储一组开放页面的表格，其中每个存储体与多个DRAM中的相应一个存储体相关联的每个存储体的当前行地址; 对于从指令处理器发出的每个指令地址，确定存储在表中的行地址和从使用该存储体号的指令处理器发出的行地址之间是否匹配，作为打开页表中的索引; 如果两个地址匹配，则以连续静态列模式继续存储器访问所指示的存储体; 并且如果两个地址不匹配，则用新的行地址覆盖表中指示的库的旧地址，并通过开始对所指示的库的新的静态列模式访问来继续存储器访问。在优选实施例中，如果在开始对所指示的银行的新的静态列模式访问之前两个地址不匹配，则必要时该方法包括中止正在进行的访问，并通知指令处理器正在中止正在进行的访问并重新开始。

2. 发明授权

US4058773A Asynchronous self timed queue 失效
标题翻译：异步自定时队列
公开(公告)号：US4058773A
公开(公告)日：1977-11-15
申请号：US666609
申请日：1976-03-15
申请人： Becky J. Clark , Charles L. Seitz
发明人： Becky J. Clark , Charles L. Seitz
IPC分类号： G11C19/28 , H03K5/15 , G11C19/00
CPC分类号： G11C19/28 , H03K5/15
摘要： An asynchronous system includes a plurality of cascaded asynchronous cells in which data is transferred through the system according to the presence of data in the cells. Each cell contains two latches for storing binary data. Means are provided for feeding back to the previous cell a signal indicative of data stored in either of the latches. Transfer gate means cooperating with the latches and the feedback data presence signal provides a means by which data is sequentially transferred through the queue according to the presence or absence of data in the cells.
摘要翻译：异步系统包括多个级联异步小区，其中根据小区中的数据的存在，通过系统传送数据。每个单元格包含两个用于存储二进制数据的锁存器。提供了用于向前一小区反馈指示存储在任一个锁存器中的数据的信号的装置。传输门装置与锁存器协作，并且反馈数据存在信号提供一种根据小区中是否有数据通过队列依次传送数据的装置。

3. 发明授权

US5047917A Apparatus for intrasystem communications within a binary n-cube including buffer lock bit 失效
标题翻译：用于在包括缓冲锁定位的二进制n-cube内进行系统间通信的装置
公开(公告)号：US5047917A
公开(公告)日：1991-09-10
申请号：US303977
申请日：1989-01-31
申请人： William C. Athas , Reese Faucette , Charles L. Seitz
发明人： William C. Athas , Reese Faucette , Charles L. Seitz
IPC分类号： G06F15/173
CPC分类号： G06F15/17343
摘要： An improved communication system for the prevention of lockup in a computer system of the binary n-cube type. Input circuitry at each of the nodes is connected for receiving messages and includes an input buffer for initially receiving the messages. Output circuitry at each of the nodes is connected for transmitting holding the messages prior to and during transmission thereof. A kernel program at each of the nodes acts as an interface between the user process programs and exclusively controls the receiving and transmitting of messages into and out of the node. There is provision for the user process programs to pass control to the kernel program to request the sending and receiving of messages by the kernel program. A lock bit is associated with each message, sensible by the user process programs, and reset by the kernel program when the kernel program has transferred the associated message. Asynchronous transfer circuitry independently and asynchronously transfers the messages as packets between the buffers of the nodes. There is logic for various decisional matters regarding message sending and receipt. There is blockout prevention logic for refusing to receive a message unless a user process program in the node has reserved a buffer of sufficient size to receive the message and for listing messages waiting to be received for which space has not yet been reserved.
摘要翻译：一种改进的通信系统，用于防止二进制n型立方体类型的计算机系统中的锁定。每个节点处的输入电路被连接用于接收消息，并且包括用于初始接收消息的输入缓冲器。在每个节点处的输出电路被连接用于发送之前和期间的发送。每个节点上的内核程序用作用户进程程序之间的接口，并专门控制消息的接收和发送进出节点。用户进程程序提供了向内核程序传递控制权以请求内核程序发送和接收消息的规定。锁定位与每个消息相关联，由用户进程程序显示，并且当内核程序传送关联的消息时由内核程序重置锁定位。异步传输电路独立且异步地将消息作为数据包传输到节点的缓冲区之间。有关消息发送和接收的各种决定事项的逻辑。除非节点中的用户处理程序已经预留了足够大小的缓冲区以接收消息并列出等待接收的空间尚未被保留的消息，否则存在用于拒绝接收消息的防止阻止逻辑。

4. 发明授权

US4156277A Access request mechanism for a serial data input/output system 失效
标题翻译：串行数据输入/输出系统的访问请求机制
公开(公告)号：US4156277A
公开(公告)日：1979-05-22
申请号：US836846
申请日：1977-09-26
申请人： Charles L. Seitz , Marshall M. Parker
发明人： Charles L. Seitz , Marshall M. Parker
IPC分类号： G06F13/26 , G06F13/374 , G06F3/00
CPC分类号： G06F13/26 , G06F13/374
摘要： An I/O data interface provides an access mechanism without requiring additional lines on the bus for device address presentation for the request of access. Each peripheral device can detect an invitation-to-request access signal and in response thereto, to supply its own device address on the bus in a serial manner with any other device requesting access. Respective device addresses are assigned to respective peripheral devices in accordance with their priority, the higher priority devices having a higher address and the lower priority devices having a lower address. If any address bit of a particular device is lower than an address bit on the bus, the device ceases to supply its address bits with the result that only the requesting device having the larger device address will be selected for communication over the I/O bus.
摘要翻译： I / O数据接口提供访问机制，而不需要总线上的附加线路用于访问请求的设备地址呈现。每个外围设备可以检测邀请请求访问信号，并且响应于此，以与请求访问的任何其他设备的串行方式在总线上提供其自己的设备地址。各个设备地址根据其优先级分配给相应的外围设备，较高优先级的设备具有较高地址，较低优先级的设备具有较低的地址。如果特定设备的任何地址位低于总线上的地址位，则设备停止提供其地址位，结果是只有具有较大设备地址的请求设备将被选择用于通过I / O总线进行通信。

5. 发明授权

US5105424A Inter-computer message routing system with each computer having separate routinng automata for each dimension of the network 失效
标题翻译：计算机间消息路由系统，每个计算机具有针对网络的每个维度的单独的自动机
公开(公告)号：US5105424A
公开(公告)日：1992-04-14
申请号：US201682
申请日：1988-06-02
申请人： Charles M. Flaig , Charles L. Seitz
发明人： Charles M. Flaig , Charles L. Seitz
IPC分类号： G06F15/173 , H04L12/56
CPC分类号： H04L45/34 , G06F15/17368 , H04L45/06
摘要： In a multicomputer, concurrent computing system having a plurality of computing nodes, this is a method and apparatus for routing message packets between the nodes. The method comprises providing a routing circuit at each node and interconnecting the routing circuits to define communications paths interconnecting the nodes along which message packets can be routed; at each routing circuit, forming routes to other nodes as a sequence of direction changing and relative address indicators for each node between the starting node and each destination node; receiving a message packet to be transmitted to another node and an associated destination node designator therefor; retrieving the route to the destination node from a memory map; adding the route to the destination node to the beginning of the message packet as part of a header; transmitting the message packet to the routing circuit of the next adjacent node on the route to the destination node; and at each intermediate node, receiving the message packet; reading the header; directing the message packet to one of two outputs thereof as a function of routing directions in the header, updating the header to reflect passage through the routing circuit; and at the destination node, stripping remaining portions of the header from the message packet; storing the message packet; and, informing the node that the message packet has arrived.
摘要翻译：在具有多个计算节点的多计算机并发计算系统中，这是在节点之间路由消息分组的方法和装置。该方法包括在每个节点处提供一个路由电路，并互连该路由电路，以定义互连各个节点的通信路径，沿着这些节点路由消息分组; 在每个路由电路中，形成到其他节点的路由，作为方向改变的序列，并且在起始节点和每个目的地节点之间的每个节点的相对地址指示符; 接收要发送到另一节点的消息分组和相关联的目的节点指示符; 从存储器映射获取到目的地节点的路由; 将作为标题的一部分的路由添加到目的地节点到消息分组的开头; 在到达目的地节点的路由上将消息分组发送到下一相邻节点的路由电路; 并在每个中间节点接收消息包; 阅读标题将消息分组指向其两个输出之一作为报头中的路由选择方向的函数，更新报头以反映通过路由电路的通过; 并且在目的地节点处，从消息分组中去除报头的剩余部分; 存储消息包; 并通知节点消息分组已经到达。

6. 发明授权

US4933933A Torus routing chip 失效
标题翻译：环形路由芯片
公开(公告)号：US4933933A
公开(公告)日：1990-06-12
申请号：US944842
申请日：1986-12-19
申请人： William J. Dally , Charles L. Seitz
发明人： William J. Dally , Charles L. Seitz
IPC分类号： G06F15/173 , H04L12/56
CPC分类号： H04L45/40 , G06F15/17337 , H04L45/06 , H04L45/20
摘要： A deadlock-free routing system for a plurality of computers ("nodes") is disclosed wherein each physical communication channel in a unidirectional multi-cycle network is split into a group of virtual channels, each channel of which has its own queue, one at each end. Packets of information traversing the same physical channel are assigned a priority as a function of the channel on which a packet arrives and the node to which the packet is destined. The packet's priority is always increasing as it moves closer and closer to its destination. Instead of reading an entire packet into an intermediate processing node before starting transmission to the next node, the routing of this invention forwards every flow control unit (flit) of the packet to the next node as soon as it arrives. The system's network is represented as a dependency graph, which graph is re-ordered to be cycle free. The resulting routing function of the cycle free channel dependency graph is rendered deadlock-free, and the system's cut-through routing results in a reduced message latency when compared under the same conditions to store-and-forward routing.
摘要翻译：公开了一种用于多个计算机（“节点”）的无死锁路由系统，其中单向多周期网络中的每个物理通信信道被分成一组虚拟信道，每个信道的每个信道具有其自己的队列，一个在每一端分配穿过相同物理信道的信息包根据分组到达的信道和分组所去往的节点的功能被分配优先级。数据包的优先级随着它越来越接近目的地而越来越多。在开始发送到下一个节点之前，不是将整个数据包读入中间处理节点，而是本发明的路由一到达就将分组的每个流控制单元（flit）转发到下一个节点。系统的网络被表示为依赖图，该图被重新排序为无循环。循环自由信道依赖关系图的结果路由功能是无死锁的，并且当在相同条件下与存储转发路由比较时，系统的直通路由导致消息延迟减少。

7. 发明授权

US4513278A Video Synthesizer for a digital video display system employing a plurality of grayscale levels displayed in discrete steps of luminance 失效
标题翻译：视频合成器，用于采用以亮度的离散步骤显示的多个灰度等级的数字视频显示系统
公开(公告)号：US4513278A
公开(公告)日：1985-04-23
申请号：US82565
申请日：1979-10-09
申请人： Charles L. Seitz , Paul Grunewald , Marshall M. Parker , Irvin G. Stafford
发明人： Charles L. Seitz , Paul Grunewald , Marshall M. Parker , Irvin G. Stafford
IPC分类号： G09G5/24 , G09G5/42 , H03K13/02
CPC分类号： G09G5/42 , G09G5/24
摘要： A digital video display system wherein the various characters to be displayed are displayed in the form of images of the complete character rather than the standard dot-matrix pattern of the prior art. A character generator in the display system stores signals representing the various characters to be displayed which are retrieved from storage in response to a character code. The signals are in the form of a binary code having a sufficient number of bits to represent a different number of levels of gray-scale or luminance values for the various picture elements making up the character image. The binary codes thus retrieved from storage are supplied to a video synthesizer that generates the video signal to display the character images which may be displayed in a number of different modes including white-on-black, black-on-white, black-on-gray, and white-on-gray as well as different combinations of such modes to represent a cursor. The video synthesizer can generate output voltage levels in discrete steps for the different luminances to be employed. The voltage output signals differ from level to level in accordance with the 2.2 root of luminance.
摘要翻译：一种数字视频显示系统，其中要显示的各种字符以完整字符的图像的形式而不是现有技术的标准点阵图案显示。显示系统中的字符发生器响应于字符代码存储表示从存储器检索的要显示的各种字符的信号。这些信号是具有足够数量的位的二进制码的形式，以表示构成字符图像的各种图像元素的不同数量的灰度级或亮度值。这样从存储器检索的二进制码被提供给视频合成器，该视频合成器产生视频信号以显示可以以黑白，黑白，黑 - 黑等多种不同模式显示的字符图像。灰色和灰白色以及这些模式的不同组合来表示光标。视频合成器可以为采用不同亮度的离散步长产生输出电压电平。电压输出信号根据亮度根数根据电平不同而不同。

8. 发明授权

US4303912A Digitally controlled composite color video display system 失效
标题翻译：数字控制复合彩色视频显示系统
公开(公告)号：US4303912A
公开(公告)日：1981-12-01
申请号：US151134
申请日：1980-05-19
申请人： Irvin G. Stafford , Charles L. Seitz
发明人： Irvin G. Stafford , Charles L. Seitz
IPC分类号： G09G1/28 , G06F3/153
CPC分类号： G09G1/285
摘要： This disclosure relates to a color video system that is adapted to receive digital codes representing values of different colors that are to be displayed to create an image on a standard video monitor. The system employs a video synthesizer which includes a memory in which appropriate digital signals are stored representing the desired transformations of the signals to signals that are to be transmitted to the video monitor. Specifically, the system is adapted to transform respective color codes to codes required for the I, Q, and Y mode of transmission.
摘要翻译：本公开涉及一种彩色视频系统，其适于接收表示将被显示以在标准视频监视器上创建图像的不同颜色的值的数字代码。该系统采用视频合成器，其包括存储器，其中存储适当的数字信号，表示将要发送到视频监视器的信号的信号的期望变换。具体地，该系统适于将各个颜色代码转换为I，Q和Y传输模式所需的代码。

9. 发明授权

US4284988A Control means to provide slow scrolling positioning and spacing in a digital video display system 失效
标题翻译：控制装置在数字视频显示系统中提供缓慢的滚动定位和间隔
公开(公告)号：US4284988A
公开(公告)日：1981-08-18
申请号：US79831
申请日：1979-09-28
申请人： Charles L. Seitz , Paul Grunewald , Marshall M. Parker , Irvin G. Stafford
发明人： Charles L. Seitz , Paul Grunewald , Marshall M. Parker , Irvin G. Stafford
IPC分类号： G09G5/24 , G09G5/28 , G09G5/40 , G06F3/14
CPC分类号： G09G5/40 , G09G5/24 , G09G5/28
摘要： This disclosure relates to a digital video display system wherein a control element is provided that includes position and count registers to specify the initial position of a scan line and the number of scan lines displayed which registers are supplied with incoming data to specify the position of each character line so that the position of a character image on display can be adjusted upwardly or downwardly to give the appearance of smooth scrolling.The various characters to be displayed are displayed in the form of images of the complete character rather than the standard dot-matrix pattern of the prior art. A character generator in the display system stores signals representing the various characters to be displayed which are retrieved from storage in response to a character code. The signals are in the form of a binary code having a sufficient number of bits to represent a different number of levels of gray-scale or luminance values for the various picture elements making up the character image.
摘要翻译：本公开涉及一种数字视频显示系统，其中提供了控制元件，其包括位置和计数寄存器，以指定扫描线的初始位置和显示的扫描线的数量，哪些寄存器被提供有输入数据以指定每个字符行，使得显示器上的字符图像的位置可以向上或向下调整以给出平滑滚动的外观。要显示的各种字符以完整字符的图像的形式显示，而不是现有技术的标准点阵图案。显示系统中的字符发生器响应于字符代码存储表示从存储器检索的要显示的各种字符的信号。这些信号是具有足够数量的位的二进制码的形式，以表示构成字符图像的各种图像元素的不同数量的灰度级或亮度值。

10. 发明授权

US4209240A Reticle exposure apparatus and method 失效
标题翻译：光罩曝光装置及方法
公开(公告)号：US4209240A
公开(公告)日：1980-06-24
申请号：US949756
申请日：1978-10-10
申请人： Ivan E. Sutherland , Charles L. Seitz
发明人： Ivan E. Sutherland , Charles L. Seitz
IPC分类号： G03F7/20 , G03B41/00
CPC分类号： G03F7/704
摘要： An apparatus and method are described for applying a light beam in an extremely precise pattern to a work piece, such as a photographic plate or reticle on which an integrated circuit pattern is to be formed and which will be then utilized to produce integrated circuits. The method includes moving a very narrow beam light source relative to the reticle in a scanning pattern such as an X-Y raster pattern, accurately sensing the relative positions of the light source to the reticle as by the use of laser interferometers, and briefly energizing the light source only when it lies at the locations to be exposed. The light source is energized while it moves, so it is not necessary to stop the light source at precisely located positions. The light source can be moved relative to the reticle, by mounting the light source on a flexible plate that oscillates in substantially a straight line, and by mounting the reticle on another flexible plate that moves perpendicular to the light source and that can be very slowly advanced perpendicular to the oscillating light source, so that after a period of time the light source has moved over every point of the reticle, although only a minority of the points normally will have been exposed.
摘要翻译：描述了一种用于以非常精确的图案将光束施加到工件（例如要在其上形成集成电路图案的照相板或标线片）上并随后用于产生集成电路的装置和方法。该方法包括以诸如XY光栅图案的扫描图案相对于掩模版移动非常窄的光束光源，通过使用激光干涉仪精确地感测光源到掩模版的相对位置，并且短暂地激励光只有当它位于要暴露的位置时才能使用。光源在移动时被通电，因此不需要在精确定位的位置停止光源。光源可以通过将光源安装在基本上直线上振荡的柔性板上，并且通过将光罩安装在垂直于光源移动的另一柔性板上并且可以非常缓慢地相对于光罩移动垂直于振荡光源前进，使得在一段时间之后光源已经移动到标线的每个点上，尽管只有少数点通常将被曝光。

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