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1. 发明授权

US5729767A System and method for accessing peripheral devices on a non-functional controller 失效
标题翻译：用于访问非功能控制器上的外围设备的系统和方法
公开(公告)号：US5729767A
公开(公告)日：1998-03-17
申请号：US319689
申请日：1994-10-07
申请人： Craig S. Jones , Victor K. Pecone , Jay Lory
发明人： Craig S. Jones , Victor K. Pecone , Jay Lory
IPC分类号： G06F11/00 , G06F11/20 , G06F11/22 , G06F11/267 , G06F11/34 , G06F13/00
CPC分类号： G06F11/1433 , G06F11/073 , G06F11/0745 , G06F11/0781 , G06F11/22 , G06F11/2236 , G06F11/006 , G06F11/2205 , G06F11/3476
摘要： A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus. Thus, if the secondary PCI bus becomes inoperable or the local processor is unable to boot, the host can still access the memory in the peripheral devices because the peripheral interface is effectively decoupled from the secondary PCI bus and the local processor. The present invention includes a host utility which can update the Flash memory, thereby providing a cost-effective and efficient mechanism for restoring code in a corrupted Flash device on a failed board. This also enables the Flash memory to be programmed for the first time during manufacturing. The system and method of the present invention allows the host CPU to access the NVRAM to obtain event failure information even if the secondary PCI bus has failed.
摘要翻译：包括主机CPU，耦合到CPU的主PCI总线和耦合到主PCI总线的总线适配器的计算机系统，其中即使总线适配器不可操作，主机CPU也可以访问包含在总线适配器中的外围设备。总线适配器包括PCI至PCI接口控制器，其包括用于耦合到主PCI总线的主PCI接口和用于耦合到辅助PCI总线的辅助PCI接口桥。外部总线接口逻辑耦合在主PCI接口和辅助PCI接口之间，并且该接口逻辑耦合到各种外围设备，包括ROM /闪存和非易失性静态随机存取存储器（NVSRAM）。根据本发明，在CPU上执行的主机实用程序可以访问外围设备，而不必访问辅助PCI总线。因此，如果辅助PCI总线变得不可操作或本地处理器无法引导，则主机仍然可以访问外围设备中的存储器，因为外围接口有效地与辅助PCI总线和本地处理器分离。本发明包括可以更新闪存的主机实用程序，从而提供用于在故障板上的损坏的闪存设备中恢复代码的成本有效且有效的机制。这也使得在制造过程中首次对闪存进行编程。本发明的系统和方法允许主机CPU访问NVRAM以获得事件故障信息，即使辅助PCI总线发生故障。

2. 发明授权

US5619728A Decoupled DMA transfer list storage technique for a peripheral resource controller 失效
标题翻译：用于外围资源控制器的去耦DMA传输列表存储技术
公开(公告)号：US5619728A
公开(公告)日：1997-04-08
申请号：US326570
申请日：1994-10-20
申请人： Craig S. Jones , Jay Lory , Victor K. Pecone
发明人： Craig S. Jones , Jay Lory , Victor K. Pecone
IPC分类号： G06F13/28 , H01J3/00
CPC分类号： G06F13/28
摘要： A peripheral resource controller such as a caching disk array controller is provided for controlling the transfer of data between a host bus and a peripheral resource, such as an array of hard disk drives. The peripheral resource controller includes a bus interface controller for providing an interface between the host bus and a local bus of the peripheral controller. The bus interface controller further includes a peripheral bus interface which accommodates accesses to a peripheral bus and a DMA controller for controlling direct memory access operations between a local memory of the peripheral controller and a system memory of the host computer. A DMA transfer list memory is coupled to the peripheral bus for storing DMA transfer information. The DMA controller fetches host and local address as well as block size information from the DMA transfer list memory to thereby effectuate DMA operations. In one specific implementation, a local processor of the peripheral controller loads the DMA transfer information into the DMA transfer list memory by causing the execution of one or more memory write cycles on the local bus. A local bus interface of the bus interface controller responds as a target and routes the data to a peripheral bus interface. The peripheral bus interface, which functions as a master of the peripheral bus, responsively effectuates corresponding cycles on the peripheral bus to write the DMA transfer information into the DMA transfer list memory.
摘要翻译：提供诸如缓存磁盘阵列控制器之类的外围资源控制器，用于控制主机总线与诸如硬盘驱动器阵列的外围资源之间的数据传输。外围资源控制器包括总线接口控制器，用于在主机总线和外围控制器的本地总线之间提供接口。总线接口控制器还包括外围总线接口，其适应对外围总线的访问和用于控制外围控制器的本地存储器与主计算机的系统存储器之间的直接存储器访问操作的DMA控制器。 DMA传输列表存储器耦合到外围总线以存储DMA传输信息。 DMA控制器从DMA传输列表存储器中获取主机和本地地址以及块大小信息，从而实现DMA操作。在一个具体实现中，外围控制器的本地处理器通过在本地总线上执行一个或多个存储器写周期来将DMA传输信息加载到DMA传输列表存储器中。总线接口控制器的本地总线接口作为目标进行响应，并将数据路由到外设总线接口。用作外设总线主机的外设总线接口响应于外设总线上的相应周期，将DMA传输信息写入DMA传输列表存储器。

3. 发明授权

US5911084A System and method for accessing peripheral devices on a non-functional controller 失效
标题翻译：用于访问非功能控制器上的外围设备的系统和方法
公开(公告)号：US5911084A
公开(公告)日：1999-06-08
申请号：US24719
申请日：1998-02-17
申请人： Craig S. Jones , Victor K. Pecone , Jay Lory
发明人： Craig S. Jones , Victor K. Pecone , Jay Lory
IPC分类号： G06F11/00 , G06F11/20 , G06F11/22 , G06F11/267 , G06F11/34 , G06F13/00
CPC分类号： G06F11/1433 , G06F11/073 , G06F11/0745 , G06F11/0781 , G06F11/22 , G06F11/2236 , G06F11/006 , G06F11/2205 , G06F11/3476
摘要： A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus. Thus, if the secondary PCI bus becomes inoperable or the local processor is unable to boot the host can still access the memory in the peripheral devices because the peripheral interface is effectively decoupled from the secondary PCI bus and the local processor. The present invention includes a host utility which can update the Flash memory, thereby providing a cost-effective and efficient mechanism for restoring code in a corrupted Flash device on a failed board. This also enables the Flash memory to be programmed for the first time during manufacturing. The system and method of the present invention allows the host CPU to access the NVRAM to obtain event failure information even if the secondary PCI bus has failed.
摘要翻译：包括主机CPU，耦合到CPU的主PCI总线和耦合到主PCI总线的总线适配器的计算机系统，其中即使总线适配器不可操作，主机CPU也可以访问包含在总线适配器中的外围设备。总线适配器包括PCI至PCI接口控制器，其包括用于耦合到主PCI总线的主PCI接口和用于耦合到辅助PCI总线的辅助PCI接口桥。外部总线接口逻辑耦合在主PCI接口和辅助PCI接口之间，并且该接口逻辑耦合到各种外围设备，包括ROM /闪存和非易失性静态随机存取存储器（NVSRAM）。根据本发明，在CPU上执行的主机实用程序可以访问外围设备，而不必访问辅助PCI总线。因此，如果辅助PCI总线变得不可操作或本地处理器无法引导，则主机仍然可以访问外围设备中的存储器，因为外围接口有效地从辅助PCI总线和本地处理器分离。本发明包括可以更新闪存的主机实用程序，从而提供用于在故障板上的损坏的闪存设备中恢复代码的成本有效且有效的机制。这也使得在制造过程中首次对闪存进行编程。本发明的系统和方法允许主机CPU访问NVRAM以获得事件故障信息，即使辅助PCI总线发生故障。

4. 发明授权

US5664119A Local proactive hot swap request/acknowledge system 失效
标题翻译：本地主动热插拔请求/确认系统
公开(公告)号：US5664119A
公开(公告)日：1997-09-02
申请号：US699016
申请日：1996-08-16
申请人： Kenneth L. Jeffries , Craig S. Jones , Victor K. Pecone
发明人： Kenneth L. Jeffries , Craig S. Jones , Victor K. Pecone
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4081
摘要： Apparatus and method for implementing a local proactive hot plug request/acknowledge scheme is disclosed. In a preferred embodiment, each hot pluggable device installable on a computer bus, such as a SCSI bus, is provided with a physical user interface comprising a mechanical request initiator, such as a button or two-position switch, for allowing a user to generate a hot swap request to a controller associated with the bus prior to actual installation of the device on, or removal of the device from, the bus. Upon receipt of the request, the controller determines whether the requested action may be performed, provides a visual indication of its determination to the user via an LED on the user interface and, if installation or removal is determined to be prudent, performs the hot installation/removal in an orderly manner so as not to adversely affect ongoing system operations.
摘要翻译：公开了用于实现本地主动式热插拔请求/确认方案的装置和方法。在优选实施例中，可安装在诸如SCSI总线的计算机总线上的每个热插拔设备都设置有物理用户界面，其包括诸如按钮或两位置开关的机械请求发起者，用于允许用户生成在将设备实际安装在总线上或从总线移除设备之前，向与总线相关联的控制器的热交换请求。在接收到请求时，控制器确定是否可以执行请求的动作，通过用户界面上的LED向用户提供其确定的可视指示，并且如果确定安全或删除是谨慎的，则执行热安装 /有秩序地移除，以免对正在进行的系统操作产生不利影响。

5. 发明授权

US5579491A Local proactive hot swap request/acknowledge system 失效
标题翻译：本地主动热插拔请求/确认系统
公开(公告)号：US5579491A
公开(公告)日：1996-11-26
申请号：US271617
申请日：1994-07-07
申请人： Kenneth L. Jeffries , Craig S. Jones , Victor K. Pecone
发明人： Kenneth L. Jeffries , Craig S. Jones , Victor K. Pecone
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4081
摘要： Apparatus and method for implementing a local proactive hot plug request/acknowledge scheme is disclosed. In a preferred embodiment, each hot pluggable device installable on a computer bus, such as a SCSI bus, is provided with a physical user interface comprising a mechanical request initiator, such as a button or two-position switch, for allowing a user to generate a hot swap request to a controller associated with the bus prior to actual installation of the device on, or removal of the device from, the bus. Upon receipt of the request, the controller determines whether the requested action may be performed, provides a visual indication of its determination to the user via an LED on the user interface and, if installation or removal is determined to be prudent, performs the hot installation/removal in an orderly manner so as not to adversely affect ongoing system operations.
摘要翻译：公开了用于实现本地主动式热插拔请求/确认方案的装置和方法。在优选实施例中，可安装在诸如SCSI总线的计算机总线上的每个热插拔设备都设置有物理用户界面，其包括诸如按钮或两位置开关的机械请求发起者，用于允许用户生成在将设备实际安装在总线上或从总线移除设备之前，向与总线相关联的控制器的热交换请求。在接收到请求时，控制器确定是否可以执行请求的动作，通过用户界面上的LED向用户提供其确定的可视指示，并且如果确定安全或删除是谨慎的，则执行热安装 /有秩序地移除，以免对正在进行的系统操作产生不利影响。

6. 发明授权

US6116176A Drag reduction assembly for use with a boat hull 失效
标题翻译：减速组件用于船体
公开(公告)号：US6116176A
公开(公告)日：2000-09-12
申请号：US375883
申请日：1999-08-17
申请人： Craig S. Jones
发明人： Craig S. Jones
IPC分类号： B63B1/34
CPC分类号： B63B1/36 , Y02T70/121
摘要： A drag-reduction system incorporated within an inwardly stepped underside of a boat hull for reducing a degree of water pressure forces exerted upon the boat hull during travel of the boat upon a body of water. A plurality of spaced apart rollers are secured at a generally aft location of the boat hull associated with the inwardly stepped underside and extend in parallel spaced apart fashion and perpendicularly to a longitudinal water flow across the boat hull experienced during propulsion of the hull. An elongate and planar shaped belt of a water impervious material having an established width and defining a continuous extending and closed loop is mounted over the plurality of spaced apart rollers. A first linearly extending location of the continuous belt is recessed within the stepped underside of the hull and a second linearly extending location is in contact with the longitudinal water flow. The second linearly extending location of the belt is capable of being translated in a direction consistent with the longitudinal water flow across the boat hull. A single drive roller or pair of drive rollers associated with the plurality of spaced apart rollers is capable of driving the belt at a velocity equal to or greater than a velocity of the longitudinal water flow traveling along the boat hull.
摘要翻译：一种减载系统，其结合在船体的向内阶梯式下侧中，用于减小在船体在水体上行进期间施加在船体上的水压力的程度。多个间隔开的辊子固定在与内侧阶梯式下侧相关联的船体的大致后部位置处，并且平行间隔地延伸并且垂直于穿过船体推进期间经受的船体的纵向水流。具有确定的宽度并限定连续的延伸和闭合的环的不透水材料的细长和平面形状的带安装在多个间隔开的辊上。连续带的第一直线延伸位置凹陷在船体的阶梯状下侧中，并且第二直线延伸位置与纵向水流接触。带的第二直线延伸位置能够在与穿过船体的纵向水流一致的方向上平移。与多个间隔开的辊相关联的单个驱动辊或一对驱动辊能够以等于或大于沿船体行进的纵向水流的速度驱动带。

7. 发明授权

US5819488A Finish floor covering utilizing single ply tiles 失效
标题翻译：使用单层砖完成地板覆盖
公开(公告)号：US5819488A
公开(公告)日：1998-10-13
申请号：US581440
申请日：1995-12-29
申请人： Craig S. Jones
发明人： Craig S. Jones
IPC分类号： E04F15/02 , E04F13/08
CPC分类号： E04F15/02
摘要： A relatively permanent and indestructible covering (10) utilizes a plurality of single ply tiles (12) which are bonded to a base floor surface (14) and provided with a protective coating in a single step by applying at least one protective bonding coating, such as an epoxy coating, over the top of plurality of tiles. To facilitate bonding to base floor surface, each of the plurality of tiles (12) are formed with a plurality of holes passing through the surface thereof. A color finish coating can also be provided over the top of the array of tiles by utilizing a protective bonding coating having a paint or paint-like quality. In a preferred embodiment, the tiles (12) are formed from a metal such as aluminum.
摘要翻译：相对永久且不可破坏的覆盖物（10）利用多个单层瓦片（12），其通过施加至少一个保护性粘合涂层，在单个步骤中结合到基底表面（14）并提供保护涂层，作为环氧树脂涂层，在多个瓷砖的顶部。为了便于与基底表面接合，多个瓷砖（12）中的每一个形成有穿过其表面的多个孔。还可以通过利用具有油漆或类似油漆的质量的保护性粘合涂层，在瓷砖阵列的顶部上提供彩色涂层。在优选实施例中，瓷砖（12）由诸如铝的金属形成。

8. 发明授权

US5617572A System for reducing power consumption in computers 失效
标题翻译：降低电脑功耗的系统
公开(公告)号：US5617572A
公开(公告)日：1997-04-01
申请号：US666059
申请日：1996-06-19
申请人： John J. Pearce , Jim Walker , Charles P. Zeller , Craig S. Jones
发明人： John J. Pearce , Jim Walker , Charles P. Zeller , Craig S. Jones
IPC分类号： G06F1/32 , G06F11/34 , G06F11/30
CPC分类号： G06F1/3215 , G06F1/325 , G06F11/3423 , G06F11/3485 , Y02B60/165
摘要： A system for reducing the amount of power consumed by a battery operated computer device is disclosed. A microcontroller continuously monitors the activity of at least one I/O device and sets an activity state variable (ASV) associated with the I/O device accordingly. Upon each the expiration of a preselected time period, the microcontroller examines the state of the ASV to determine whether the I/O device was active during the expired time period. If so, the I/O device is caused to operate in a full power mode; otherwise, the I/O device is caused to operate in a reduced power consumption mode. In one embodiment, the I/O device is capable of operating in more than one reduced power consumption mode, in which case, responsive to a determination that the I/O device was not active during the expired time period, the I/O device is caused to operate in the next lowest power consumption mode. In an alternative embodiment, the frequency with which timer interrupts are generated is automatically adjusted after the expiration of each time period.
摘要翻译：公开了一种用于减少由电池供电的计算机设备消耗的功率量的系统。微控制器连续地监视至少一个I / O设备的活动，并相应地设置与I / O设备相关联的活动状态变量（ASV）。在每个预选时间段到期后，微控制器检查ASV的状态，以确定在过期时间段期间I / O设备是否处于活动状态。如果是这样，则使I / O设备在全功率模式下工作; 否则，使得I / O设备以降低的功耗模式工作。在一个实施例中，I / O设备能够以多于一个的降低功耗模式进行操作，在这种情况下，响应于I / O设备在到期时间段期间不活动的确定，I / O设备导致在下一个最低功耗模式下运行。在替代实施例中，在每个时间段到期之后，自动调整产生定时器中断的频率。

9. 发明授权

US5581740A System for reading CD ROM data from hard disks 失效
标题翻译：从硬盘读取CD ROM数据的系统
公开(公告)号：US5581740A
公开(公告)日：1996-12-03
申请号：US317510
申请日：1994-10-04
申请人： Craig S. Jones
发明人： Craig S. Jones
IPC分类号： G06F3/06 , G11C29/00 , G06F13/00
CPC分类号： G06F3/0601 , G06F2003/0694 , G06F2003/0697 , G11C29/74
摘要： A CD ROM server comprises a CD ROM drive and an array of hard disk drives. Means are provided for copying data from the CD ROM drive to the array of hard disk drives, and for deleting data from the array of hard disk drives, upon receipt of copy and delete requests, respectively, from a host computer system. Means are provided for the host computer to read data from the array of hard disk drives in the CD ROM format that the data had been stored in on the CD ROM. Means are also available to implement RAID technology with the array of hard disk drives for data reconstruction, striping, and redundancy. Means may be provided for the host computer to communicate directly with any SCSI devices connected to the server.
摘要翻译： CD ROM服务器包括CD ROM驱动器和硬盘驱动器阵列。提供了用于将数据从CD ROM驱动器复制到硬盘驱动器阵列的装置，并且用于从主计算机系统分别接收到复制和删除请求时从硬盘驱动器阵列中删除数据。提供了用于主计算机从CD ROM格式的数据已经存储在CD ROM上的硬盘驱动器阵列读取数据的装置。还可以使用硬盘驱动器阵列实现RAID技术，用于数据重建，条带化和冗余。可以提供用于主计算机与连接到服务器的任何SCSI设备直接通信的装置。

10. 发明授权

US5619723A System for scheduling read ahead operations if new request is sequential of last n last read requests wherein n is different on independent activities 失效
标题翻译：用于调度预读操作的系统，如果新请求是最后n个最后读取请求的顺序，其中n在独立活动上不同
公开(公告)号：US5619723A
公开(公告)日：1997-04-08
申请号：US562238
申请日：1995-11-21
申请人： Craig S. Jones , Kenneth L. Jeffries , Terry J. Parks
发明人： Craig S. Jones , Kenneth L. Jeffries , Terry J. Parks
IPC分类号： G06F3/06 , G06F12/08 , G11B20/18 , G06F13/14
CPC分类号： G06F3/0601 , G06F12/0862 , G11B20/1833 , G11B20/1883 , G06F12/0866 , G06F2003/0697 , G06F2212/6026 , G11B2220/20
摘要： A disk drive array with a controller which provides: dynamic remapping for grown defects in the disk drives, multi-thread request processing with a variable number of forkings, defect tracking with both logical and physical lists, guarded writes of less than a full stripe optimized by selectably using the redundancy to limit the number of sectors involved, association of multiple operations with a single disk request in order to facilitate error handling, use of an access hiatus as indication of further opportunity to rebuild data in background, and scatter/scatter (bidirectional scatter/gather) operations.
摘要翻译：具有控制器的磁盘驱动器阵列，其提供：用于磁盘驱动器中的长期缺陷的动态重映射，具有可变数量的分叉的多线程请求处理，具有逻辑和物理列表的缺陷跟踪，小于全条带优化的保护写入通过可选择地使用冗余来限制涉及的扇区数量，多个操作与单个磁盘请求的关联以便于错误处理，使用访问间隙作为在后台重建数据的进一步机会的指示以及散射/散射（双向分散/聚合）操作。

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