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1. 发明授权

US07960234B2 Multiple-gate MOSFET device and associated manufacturing methods 有权
标题翻译：多栅MOSFET器件及相关制造方法
公开(公告)号：US07960234B2
公开(公告)日：2011-06-14
申请号：US11726516
申请日：2007-03-22
申请人： Craig Henry Huffman , Weize Xiong , Cloves Rinn Cleavelin
发明人： Craig Henry Huffman , Weize Xiong , Cloves Rinn Cleavelin
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/7853
摘要： One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby exposing at least one surface of a first gate electrode material. The exposed surface of the first gate electrode material is deglazed. Subsequently, the first gate electrode material is removed. Other methods and devices are also disclosed.
摘要翻译：本发明的一个实施例涉及一种制造多栅极晶体管的方法。在该方法期间，从形成多栅极晶体管的半导体结构中选择性地去除第二栅电极材料，从而暴露第一栅电极材料的至少一个表面。第一栅电极材料的暴露表面被去角质化。随后，去除第一栅电极材料。还公开了其它方法和装置。

2. 发明申请

US20080233697A1 Multiple-gate MOSFET device and associated manufacturing methods 有权
标题翻译：多栅MOSFET器件及相关制造方法
公开(公告)号：US20080233697A1
公开(公告)日：2008-09-25
申请号：US11726516
申请日：2007-03-22
申请人： Craig Henry Huffman , Weize Xiong , Cloves Rinn Cleavelin
发明人： Craig Henry Huffman , Weize Xiong , Cloves Rinn Cleavelin
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/7853
摘要： One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby exposing at least one surface of a first gate electrode material. The exposed surface of the first gate electrode material is deglazed. Subsequently, the first gate electrode material is removed. Other methods and devices are also disclosed.
摘要翻译：本发明的一个实施例涉及一种制造多栅极晶体管的方法。在该方法期间，从形成多栅极晶体管的半导体结构中选择性地去除第二栅电极材料，从而暴露第一栅极电极材料的至少一个表面。第一栅电极材料的暴露表面被去角质化。随后，去除第一栅电极材料。还公开了其它方法和装置。

3. 发明申请

US20120175710A1 INTEGRATED CIRCUITS WITH ALIGNED (100) NMOS AND (110) PMOS FINFET SIDEWALL CHANNELS 有权
标题翻译：具有对准（100）NMOS和（110）PMOS FinFET平台通道的集成电路
公开(公告)号：US20120175710A1
公开(公告)日：2012-07-12
申请号：US13425082
申请日：2012-03-20
申请人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
发明人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
IPC分类号： H01L27/092
CPC分类号： H01L27/0886 , G11C11/412 , H01L21/823807 , H01L21/823821 , H01L27/0207 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/045 , Y10S257/90 , Y10S438/973 , Y10S438/982
摘要： An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orientations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.
摘要翻译：公开了一种包括多个多栅极FinFET（MuGFET）的集成电路器件。通过在直接硅键合（DSB）混合取向技术（HOT）衬底上的非晶化和晶体再生长形成用于PMOS和NMOS MuGFET的不同晶体取向的晶片。 PMOS MuGFET翅片由具有（110）晶体取向的翅片侧壁表面限定的通道形成。 NMOS MuGFET翅片由曼哈顿布局具有（100）晶体取向的翅片侧壁表面限定的通道形成，其中不同PMOS和NMOS MuGFET的侧壁通道以0°或90°旋转对准。

4. 发明授权

US07683417B2 Memory device with memory cell including MuGFET and fin capacitor 有权
标题翻译：具有存储单元的存储器件包括MuGFET和鳍式电容器
公开(公告)号：US07683417B2
公开(公告)日：2010-03-23
申请号：US11924817
申请日：2007-10-26
申请人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
发明人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
IPC分类号： H01L27/108
CPC分类号： H01L29/94 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L28/60 , H01L29/785 , H01L29/7855
摘要： One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.
摘要翻译：本发明的一个实施例涉及一种存储单元。存储单元包括与半导体鳍片的第一区域相关联的多栅极场效应晶体管。存储单元还包括耦合到多栅极场效应晶体管的漏极并与半导体鳍片的第二区域相关联的散热片电容器，其中散热片电容器在第二区域中具有大致简并掺杂浓度。还公开了其它装置和方法。

5. 发明申请

US20080303095A1 VARYING MUGFET WIDTH TO ADJUST DEVICE CHARACTERISTICS 审中-公开
标题翻译：改变MUGFET宽度以调整设备特性
公开(公告)号：US20080303095A1
公开(公告)日：2008-12-11
申请号：US11759710
申请日：2007-06-07
申请人： Weize Xiong , Cloves Rinn Cleavelin
发明人： Weize Xiong , Cloves Rinn Cleavelin
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L2029/7857
摘要： One embodiment of the present invention relates to an integrated circuit that includes a first multi-gate transistor that has a first fin width and a first threshold voltage. The integrated circuit also includes a second multi-gate transistor that has a second fin width that is greater than the first width and a second threshold voltage that is less than the first threshold voltage. Other circuits and methods are also disclosed.
摘要翻译：本发明的一个实施例涉及一种集成电路，其包括具有第一鳍宽度和第一阈值电压的第一多栅极晶体管。集成电路还包括具有大于第一宽度的第二鳍宽度和小于第一阈值电压的第二阈值电压的第二多栅极晶体管。还公开了其它电路和方法。

6. 发明授权

US07897994B2 Method of making (100) NMOS and (110) PMOS sidewall surface on the same fin orientation for multiple gate MOSFET with DSB substrate 有权
标题翻译：制造具有DSB衬底的多栅极MOSFET的（100）NMOS和（110）PMOS侧壁表面的方法
公开(公告)号：US07897994B2
公开(公告)日：2011-03-01
申请号：US11764442
申请日：2007-06-18
申请人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
发明人： Weize Xiong , Cloves Rinn Cleavelin , Angelo Pinto , Rick L. Wise
IPC分类号： H01L29/66
CPC分类号： H01L27/0886 , G11C11/412 , H01L21/823807 , H01L21/823821 , H01L27/0207 , H01L27/092 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/045 , Y10S257/90 , Y10S438/973 , Y10S438/982
摘要： A method of forming an integrated circuit device that includes a plurality of MuGFETs is disclosed. A PMOS fin of a MuGFET is formed on a substrate. The PMOS fin includes a channel of a first surface of a first crystal orientation. A NMOS fin of another MuGFET is formed on the substrate. The NMOS fin includes a channel on the substrate at one of 0° and 90° to the PMOS fin and includes a second surface of a second crystal orientation.
摘要翻译：公开了一种形成包括多个MuGFET的集成电路器件的方法。在基板上形成MuGFET的PMOS鳍。 PMOS鳍包括第一晶体取向的第一表面的沟道。在基板上形成另一个MuGFET的NMOS鳍。所述NMOS鳍片包括在所述衬底上与所述PMOS鳍片0°和90°之一处的通道，并且包括第二晶体取向的第二表面。

7. 发明申请

US20090253253A1 METHOD OF ADJUSTING FDSOI THRESHOLD VOLTAGE THROUGH OXIDE CHARGES GENERATION IN THE BURIED OXIDE 有权
标题翻译：通过氧化硅氧化物生成的氧化物电压调节方法
公开(公告)号：US20090253253A1
公开(公告)日：2009-10-08
申请号：US12062968
申请日：2008-04-04
申请人： Weize XIONG , Cloves Rinn Cleavelin
发明人： Weize XIONG , Cloves Rinn Cleavelin
IPC分类号： H01L21/425
CPC分类号： H01L21/31155 , H01L21/26506 , H01L21/28211 , H01L21/823842 , H01L21/823878 , H01L21/84
摘要： Different performance MOSFET Fully Depleted devices can be achieved on a single chip by varying the Vt through ion implantation. The integration of multiple Vt can be achieved through the selection of a metal gate stack with suitable effective WF for one semiconductor device to be included on a chip. Then, an ion implantation, with a dopant such as F, can be selectively performed to achieve proper Vt for other semiconductor devices on the chip.
摘要翻译：通过改变Vt通过离子注入，可以在单个芯片上实现不同性能的MOSFET完全耗尽的器件。可以通过选择具有合适的有效WF的金属栅极堆叠来实现多个Vt的集成，一个半导体器件将被包括在芯片上。然后，可以选择性地执行具有诸如F的掺杂剂的离子注入，以为芯片上的其它半导体器件实现适当的Vt。

8. 发明申请

US20090108316A1 MEMORY DEVICE WITH MEMORY CELL INCLUDING MUGFET AND FIN CAPACITOR 有权
标题翻译：具有包含MUGFET和FIN电容器的存储器单元的存储器件
公开(公告)号：US20090108316A1
公开(公告)日：2009-04-30
申请号：US11924817
申请日：2007-10-26
申请人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
发明人： Weize Xiong , Andrew Marshall , Cloves Rinn Cleavelin , Howard Lee Tigelaar
IPC分类号： H01L29/94
CPC分类号： H01L29/94 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L28/60 , H01L29/785 , H01L29/7855
摘要： One embodiment of the present invention relates to a memory cell. The memory cell includes a multi-gate field effect transistor associated with a first region of a semiconductor fin. The memory cell also includes a fin capacitor coupled to a drain of the multi-gate field effect transistor and associated with a second region of the semiconductor fin, where the fin capacitor has an approximately degenerate doping concentration in the second region. Other devices and methods are also disclosed.
摘要翻译：本发明的一个实施例涉及一种存储单元。存储单元包括与半导体鳍片的第一区域相关联的多栅极场效应晶体管。存储单元还包括耦合到多栅极场效应晶体管的漏极并与半导体鳍片的第二区域相关联的散热片电容器，其中散热片电容器在第二区域中具有大致简并掺杂浓度。还公开了其它装置和方法。

9. 发明授权

US08581317B2 SOI MuGFETs having single gate electrode level 有权
标题翻译：具有单栅电极层的SOI MuGFET
公开(公告)号：US08581317B2
公开(公告)日：2013-11-12
申请号：US12199041
申请日：2008-08-27
申请人： Howard Tigelaar , Cloves Rinn Cleavelin , Andrew Marshall , Weize Xiong
发明人： Howard Tigelaar , Cloves Rinn Cleavelin , Andrew Marshall , Weize Xiong
IPC分类号： H01L27/115
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11519 , H01L27/11521 , H01L27/11558
摘要： A silicon on insulator (SOI) multi-gate field effect transistor electrically Programmable Read-Only Memory (MuFET EPROM) includes a substrate having a dielectric surface. A first semiconducting region is in or on the dielectric surface. A source region, a drain region and a channel region interposed between the source and drain are formed in first semiconducting region. A gate dielectric layer is on the channel region. At least a second semiconducting region in or on the dielectric surface is spaced apart from the first semiconducting region. A first electrode layer comprises a first electrode portion including a transistor gate electrode and a control gate electrode electrically isolated from one another. The transistor gate overlies the channel region to form a transistor. The control gate extends to overlay a portion of the second semiconducting region. The transistor gate and thus the transistor and the control gate are capacitively coupled to one another by at least one MOS coupling capacitor, with one plate of the MOS coupling capacitor ohmically coupled to or including the second semiconducting region.
摘要翻译：绝缘体上硅（SOI）多栅极场效应晶体管电可编程只读存储器（MuFET EPROM）包括具有电介质表面的衬底。第一半导电区域位于电介质表面中或其上。源极区域，漏极区域和介于源极和漏极之间的沟道区域形成在第一半导体区域中。栅介质层位于沟道区上。电介质表面中或电介质表面上的至少第二半导体区域与第一半导体区域间隔开。第一电极层包括第一电极部分，其包括晶体管栅电极和彼此电隔离的控制栅电极。晶体管栅极覆盖沟道区以形成晶体管。控制门延伸以覆盖第二半导体区域的一部分。晶体管栅极，因此晶体管和控制栅极通过至少一个MOS耦合电容器彼此电容耦合，MOS耦合电容的一个板欧姆耦合到或包括第二半导体区域。

10. 发明授权

US07939393B2 Method of adjusting FDSOI threshold voltage through oxide charges generation in the buried oxide 有权
标题翻译：通过掩埋氧化物中氧化物电荷产生来调整FDSOI阈值电压的方法
公开(公告)号：US07939393B2
公开(公告)日：2011-05-10
申请号：US12062968
申请日：2008-04-04
申请人： Weize Xiong , Cloves Rinn Cleavelin
发明人： Weize Xiong , Cloves Rinn Cleavelin
IPC分类号： H01L21/337
CPC分类号： H01L21/31155 , H01L21/26506 , H01L21/28211 , H01L21/823842 , H01L21/823878 , H01L21/84
摘要： Different performance MOSFET Fully Depleted devices can be achieved on a single chip by varying the Vt through ion implantation. The integration of multiple Vt can be achieved through the selection of a metal gate stack with suitable effective WF for one semiconductor device to be included on a chip. Then, an ion implantation, with a dopant such as F, can be selectively performed to achieve proper Vt for other semiconductor devices on the chip.
摘要翻译：通过改变Vt通过离子注入，可以在单个芯片上实现不同性能的MOSFET完全耗尽的器件。可以通过选择具有合适的有效WF的金属栅极堆叠来实现多个Vt的集成，一个半导体器件将被包括在芯片上。然后，可以选择性地执行具有诸如F的掺杂剂的离子注入，以为芯片上的其它半导体器件实现适当的Vt。

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