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1. 发明授权

US06990030B2 Magnetic memory having a calibration system 有权
标题翻译：具有校准系统的磁存储器
公开(公告)号：US06990030B2
公开(公告)日：2006-01-24
申请号：US10690249
申请日：2003-10-21
申请人： Connie Lemus , Kenneth Kay Smith , Frederick A. Perner , Robert Sesek
发明人： Connie Lemus , Kenneth Kay Smith , Frederick A. Perner , Robert Sesek
IPC分类号： G11C7/02 , G11C7/04
CPC分类号： G11C29/02 , G11C11/16 , G11C29/026 , G11C29/028 , G11C2029/5002
摘要： A magnetic memory having a calibration system is disclosed. One embodiment of the magnetic memory includes a sense amplifier and a calibration system configured to monitor at least one operating parameter of the magnetic memory and calibrate the sense amplifier if a measured parameter corresponding to the at least one operating parameter is within a range.
摘要翻译：公开了一种具有校准系统的磁存储器。磁存储器的一个实施例包括读出放大器和校准系统，其被配置为监测磁存储器的至少一个操作参数，并且如果对应于至少一个操作参数的测量参数在范围内，则校准读出放大器。

2. 发明授权

US07290118B2 Address control system for a memory storage device 有权
标题翻译：用于存储器存储设备的地址控制系统
公开(公告)号：US07290118B2
公开(公告)日：2007-10-30
申请号：US10754663
申请日：2004-01-08
申请人： Kenneth Kay Smith , Sarah Morris Brandenberger , Terrel Munden , Frederick A. Perner , Connie Lemus , David McIntyre
发明人： Kenneth Kay Smith , Sarah Morris Brandenberger , Terrel Munden , Frederick A. Perner , Connie Lemus , David McIntyre
IPC分类号： G06F12/00
CPC分类号： G11C7/1048 , G11C8/12
摘要： A memory storage device having an address control system is disclosed. The memory storage device includes memory cells and an address control system configured to decode a bit number which identifies a number of the memory cells which are selected in parallel. The memory cells selected in parallel correspond to least significant bits of an address which has a range that includes the memory cells.
摘要翻译：公开了一种具有地址控制系统的存储器存储设备。存储器存储设备包括存储器单元和地址控制系统，该地址控制系统被配置为解码识别并行选择的存储器单元的数量的位数。并行选择的存储单元对应于具有包括存储单元的范围的地址的最低有效位。

3. 发明授权

US07079436B2 Resistive cross point memory 有权
标题翻译：电阻式交叉点存储器
公开(公告)号：US07079436B2
公开(公告)日：2006-07-18
申请号：US10675740
申请日：2003-09-30
申请人： Frederick A. Perner , Kenneth Kay Smith
发明人： Frederick A. Perner , Kenneth Kay Smith
IPC分类号： G11C7/02
CPC分类号： G11C29/02 , G11C7/02 , G11C11/1673 , G11C29/026 , G11C29/028 , G11C2207/2254
摘要： Embodiments of the present invention provide a resistive cross point memory. The resistive cross point memory comprises an array of memory cells and a read circuit. The read circuit is configured to sense a resistance through a memory cell in the array of memory cells to obtain a sense result and calibrate the read circuit based on the sensed result. The read circuit comprises an up/down counter that provides a calibration value to the read circuit.
摘要翻译：本发明的实施例提供一种电阻式交叉点存储器。电阻交叉点存储器包括存储器单元阵列和读取电路。读取电路被配置为感测通过存储器单元阵列中的存储器单元的电阻以获得感测结果，并且基于感测结果来校准读取电路。读取电路包括向读取电路提供校准值的向上/向下计数器。

4. 发明授权

US06842364B1 Memory cell strings in a resistive cross point memory cell array 有权
标题翻译：电阻交叉点存储单元阵列中的存储单元串
公开(公告)号：US06842364B1
公开(公告)日：2005-01-11
申请号：US10614505
申请日：2003-07-07
申请人： Richard Le Hilton , Corbin Champion , Kenneth Kay Smith , Frederick A. Perner
发明人： Richard Le Hilton , Corbin Champion , Kenneth Kay Smith , Frederick A. Perner
IPC分类号： G11C11/15 , G11C5/00 , G11C7/22 , G11C11/00 , G11C11/02 , G11C11/16 , G11C16/04
CPC分类号： G11C11/16
摘要： A method for performing a read operation from a memory cell in a memory cell is provided. The method includes applying a constant current across the memory cell string, measuring a first voltage across the memory cell string, writing the memory cell to a first state, measuring a second voltage across the memory cell string, and determining whether the first voltage differs from the second voltage.
摘要翻译：提供了一种用于从存储单元中的存储单元执行读取操作的方法。该方法包括在存储单元串中施加恒定电流，测量存储单元串两端的第一电压，将存储单元写入第一状态，测量存储单元串两端的第二电压，以及确定第一电压是否与第二电压。

5. 发明授权

US06829191B1 Magnetic memory equipped with a read control circuit and an output control circuit 有权
标题翻译：磁记忆体配有读控制电路和输出控制电路
公开(公告)号：US06829191B1
公开(公告)日：2004-12-07
申请号：US10726393
申请日：2003-12-03
申请人： Frederick A. Perner , Kenneth Kay Smith , Sarah Morris Brandenberger
发明人： Frederick A. Perner , Kenneth Kay Smith , Sarah Morris Brandenberger
IPC分类号： G11C700
CPC分类号： G11C11/16
摘要： A magnetic memory is disclosed. In one embodiment, the magnetic memory includes first and second memory cells and a read controller coupled to the first and second memory cells. An output controller coupled to the read controller and to the first and second memory cells, wherein the output controller is configured to receive read data in parallel only from the first or second memory cells which have completed the current read operation regardless of whether both the first and second memory cells have completed the current read operation and convert the parallel data to serial data and shift the parallel data to an output in synchronism with the system clock signal.
摘要翻译：公开了磁存储器。在一个实施例中，磁存储器包括耦合到第一和第二存储器单元的第一和第二存储器单元和读取控制器。耦合到读控制器和第一和第二存储器单元的输出控制器，其中输出控制器被配置为仅从已完成当前读操作的第一或第二存储器单元并行地接收读数据，而不管第一并且第二存储单元已经完成当前的读取操作，并且将并行数据转换成串行数据，并且将并行数据与系统时钟信号同步地移位到输出端。

6. 发明授权

US06873543B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US06873543B2
公开(公告)日：2005-03-29
申请号：US10448574
申请日：2003-05-30
申请人： Kenneth Kay Smith , Andrew VanBrocklin , Peter Fricke , Frederick A. Perner , Kenneth James Eldredge
发明人： Kenneth Kay Smith , Andrew VanBrocklin , Peter Fricke , Frederick A. Perner , Kenneth James Eldredge
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15 , G11C11/16 , G11C29/50
CPC分类号： G11C29/026 , G11C11/16 , G11C29/028 , G11C29/50
摘要： Embodiments of the present invention provide a memory device. In one embodiment, the memory device comprises an array of memory cells configured to provide resistive states, a read circuit configured to sense the resistive states and a resistor. The resistor is configured to provide a resistance to the read circuit that is configured to select the resistor and sense the resistance to test the read circuit.
摘要翻译：本发明的实施例提供一种存储装置。在一个实施例中，存储器件包括被配置为提供电阻状态的存储器单元的阵列，被配置为感测电阻状态的读取电路和电阻器。电阻器被配置为提供对被配置为选择电阻器并且感测电阻以测试读取电路的读取电路的电阻。

7. 发明授权

US06847544B1 Magnetic memory which detects changes between first and second resistive states of memory cell 有权
标题翻译：磁存储器，用于检测存储器单元的第一和第二电阻状态之间的变化
公开(公告)号：US06847544B1
公开(公告)日：2005-01-25
申请号：US10689144
申请日：2003-10-20
申请人： Kenneth Kay Smith , Frederick A. Perner , Richard Lee Hilton
发明人： Kenneth Kay Smith , Frederick A. Perner , Richard Lee Hilton
IPC分类号： G11C11/14 , G11C11/00
CPC分类号： G11C11/14
摘要： A magnetic memory which detects changes between resistive states of a memory cell is disclosed. In one embodiment the magnetic memory includes a memory cell which has first and second resistive states. First and second write conductors are configured to conduct first and second currents to change the memory cell between the first and the second resistive states. The first and the second write conductors are routed in first and second directions and intersect the memory cell. First and second sense conductors are configured to conduct a sense current through the memory cell. A sense circuit coupled to the second sense conductor is configured to detect the change between the first and the second resistive states.
摘要翻译：公开了一种用于检测存储器单元的电阻状态之间的变化的磁存储器。在一个实施例中，磁存储器包括具有第一和第二电阻状态的存储单元。第一和第二写入导体被配置为传导第一和第二电流以改变第一和第二电阻状态之间的存储单元。第一和第二写导体在第一和第二方向上布线，并与存储单元相交。第一和第二感测导体被配置为通过存储器单元传导感测电流。耦合到第二感测导体的感测电路被配置为检测第一和第二电阻状态之间的变化。

8. 发明授权

US06894938B2 System and method of calibrating a read circuit in a magnetic memory 有权
标题翻译：在磁存储器中校准读取电路的系统和方法
公开(公告)号：US06894938B2
公开(公告)日：2005-05-17
申请号：US10678322
申请日：2003-10-03
申请人： Kenneth Kay Smith , Frederick A. Perner , Richard L. Hilton
发明人： Kenneth Kay Smith , Frederick A. Perner , Richard L. Hilton
IPC分类号： G11C11/15 , G11C29/50 , G11C29/00
CPC分类号： G11C29/50 , G11C11/15
摘要： A system and method of calibrating a read circuit in a magnetic memory is disclosed. In one embodiment, the method includes measuring a calibration value. A large error calibration is performed if the calibration value is within a maximum range. A small error calibration is performed if the calibration value is within a minimum range. The method may include performing a first read operation on the magnetic memory, and performing a second read operation on the magnetic memory.
摘要翻译：公开了一种校准磁存储器中的读取电路的系统和方法。在一个实施例中，该方法包括测量校准值。如果校准值在最大范围内，则执行较大的误差校准。如果校准值在最小范围内，则执行小误差校准。该方法可以包括对磁存储器执行第一读取操作，以及对磁存储器执行第二读取操作。

9. 发明授权

US06990012B2 Magnetic memory device 有权
标题翻译：磁存储器件
公开(公告)号：US06990012B2
公开(公告)日：2006-01-24
申请号：US10680464
申请日：2003-10-07
申请人： Kenneth Kay Smith , Frederick A. Perner
发明人： Kenneth Kay Smith , Frederick A. Perner
IPC分类号： G11C11/00
CPC分类号： H01L27/222 , G11C11/16
摘要： The present invention provides a magnetic memory. In one embodiment, the magnetic memory includes a first line having a first cross-sectional area. A second line is provided having a second cross-sectional area different from the first cross-sectional area. A magnetic memory cell stack is positioned between the first line and the second line.
摘要翻译：本发明提供一种磁存储器。在一个实施例中，磁存储器包括具有第一横截面积的第一线。提供具有不同于第一横截面积的第二横截面积的第二线。磁存储单元堆叠位于第一线和第二线之间。

10. 发明授权

US06891768B2 Power-saving reading of magnetic memory devices 有权
标题翻译：磁存储器件的省电读取
公开(公告)号：US06891768B2
公开(公告)日：2005-05-10
申请号：US10293027
申请日：2002-11-13
申请人： Kenneth Kay Smith , Frederick A. Perner
发明人： Kenneth Kay Smith , Frederick A. Perner
IPC分类号： G11C7/06 , G11C11/16 , G11C7/02
CPC分类号： G11C7/062 , G11C11/1673 , G11C13/0061 , G11C27/022 , G11C2013/0057
摘要： Power-saving reading of magnetic memory devices. In one arrangement, a method includes pulsing a voltage on the array, and obtaining a voltage value indicative of a memory state of the target memory cell from the voltage pulse using a sensing circuit that is electrically connected to the target memory cell. In another arrangement, a method includes pulsing an array voltage on a plurality of row and column conductors of the array, connecting a sensing circuit to a conductor that is electrically coupled to the target memory cell, the sensing circuit including a sense element, and determining the voltage drop across the sense element of the sensing circuit during the voltage pulse, the voltage drop being indicative of a memory state of the target memory cell.
摘要翻译：磁存储器件的省电读取。在一种布置中，一种方法包括使阵列上的电压脉冲，并使用电连接到目标存储单元的感测电路从电压脉冲获得指示目标存储单元的存储状态的电压值。在另一种布置中，一种方法包括在阵列的多个行和列导体上脉冲阵列电压，将感测电路连接到电耦合到目标存储单元的导体，感测电路包括感测元件，以及确定电压脉冲期间感测电路的感测元件上的电压降，电压降指示目标存储器单元的存储状态。

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