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1. 发明授权

US4864375A Dram cell and method 失效
标题翻译：戏剧细胞和方法
公开(公告)号：US4864375A
公开(公告)日：1989-09-05
申请号：US188729
申请日：1988-04-29
申请人： Clarence W. Teng , Cheng-Eng D. Chen , Bor-Yen Mao
发明人： Clarence W. Teng , Cheng-Eng D. Chen , Bor-Yen Mao
IPC分类号： H01L27/108
CPC分类号： H01L27/10841
摘要： The following detailed description describes a dynamic random access memory (dRAM) cell. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell pass transistor is formed on the sidewalls of a trench containing the cell capacitor; the word and bit lines cross over this trench. The trench extends through an epitaxial layer into a substrate. The epitaxial layer and substrate are separated by a layer which serves as a diffusion barrier. This stacking of the transistor on top of the capcitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. The diffusion barrier allows for the optimal doping of the epitaxial for operation of the transistor and optimal doping of the substrate for operation of the capacitor.One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench, and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is transferred to the polysilicon capacitor plate transistor with the polysilicon capacitor plate. This connection between source and polysilicon capacitor plate is provided by a buried lateral contact.
摘要翻译：以下详细描述描述了动态随机存取存储器（dRAM）单元。所述单元提供单晶体管/单电容器dRAM单元结构和阵列，其中单元传输晶体管形成在包含单元电容器的沟槽的侧壁上; 字和位线跨过这个沟槽。沟槽延伸穿过外延层进入衬底。外延层和衬底被用作扩散阻挡层的层分开。晶体管在电容器顶部的堆叠产生了在衬底上具有最小面积的电池，并且解决了电池致密堆积的问题。扩散势垒允许用于晶体管的操作的外延的最佳掺杂和用于电容器操作的衬底的最佳掺杂。一个电容器板和晶体管沟道和源极区域形成在沟槽的体侧壁中，并且晶体管栅极和电容器的另一个栅极都形成在沟槽中的多晶硅中，但是在其内部的氧化物层彼此分开沟。信号电荷用多晶硅电容器板转移到多晶硅电容器板晶体管。源极和多晶硅电容器板之间的这种连接由埋入的侧面接触提供。

2. 发明授权

US5026656A MOS transistor with improved radiation hardness 失效
标题翻译：具有改善辐射硬度的MOS晶体管
公开(公告)号：US5026656A
公开(公告)日：1991-06-25
申请号：US488360
申请日：1990-03-02
申请人： Mishel Matloubian , Cheng-Eng D. Chen , Terence G. Blake
发明人： Mishel Matloubian , Cheng-Eng D. Chen , Terence G. Blake
IPC分类号： H01L21/74 , H01L23/482 , H01L29/786
CPC分类号： H01L23/4825 , H01L21/743 , H01L29/78609 , H01L29/78612 , H01L2924/0002 , Y10S438/953
摘要： An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.
摘要翻译：公开了一种MOS晶体管，其具有用于在暴露于电离辐射之后通过隔离氧化物防止源极至漏极导通的保护环。在所描述的n沟道晶体管的例子中，相对于栅电极以自对准的方式在源极区域的边缘处形成p +区域，以便不在栅极下方延伸以接触漏极区域。即使在栅电极与场氧化物重叠的隔离场氧化物下面形成沟道，该p +区形成二极管，其阻止源 - 漏导通。该结构可以被硅化以提高串联电阻。还公开了以SOI配置形成的晶体管的示例。

3. 发明授权

US5166770A Silicided structures having openings therein 失效
标题翻译：其中有开孔的硅化结构
公开(公告)号：US5166770A
公开(公告)日：1992-11-24
申请号：US38394
申请日：1987-04-15
申请人： Thomas E. Tang , Che-Chia Wei , Cheng-Eng D. Chen
发明人： Thomas E. Tang , Che-Chia Wei , Cheng-Eng D. Chen
IPC分类号： H01L21/285 , H01L21/8238 , H01L23/532 , H01L27/092 , H01L29/78
CPC分类号： H01L21/285 , H01L23/53257 , H01L27/0928 , H01L2924/0002
摘要： Preferred embodiments include silicon complementary MOSFETs with titanium silicided junctions (38, 58) and direct contacts of aluminum metallization (61, 62) to the p junctions (58) which avoids the high contact resistance of the silicide (60) to p silicon (58). Preferred embodiments also include silicided polysilicon lines without corresponding silicided MOSFET junctions.
摘要翻译：优选实施例包括具有钛硅化物结（38,58）的硅互补MOSFET和铝金属化（61,62）与p结（58）的直接接触，避免了硅化物（60）对p硅（58）的高接触电阻）。优选实施例还包括没有相应的硅化MOSFET结的硅化多晶硅线。

4. 发明授权

US5047361A NMOS transistor having inversion layer source/drain contacts 失效
标题翻译： NMOS晶体管具有反向层源极/漏极触点
公开(公告)号：US5047361A
公开(公告)日：1991-09-10
申请号：US549507
申请日：1990-07-06
申请人： Mishel Matloubian , Cheng-Eng D. Chen
发明人： Mishel Matloubian , Cheng-Eng D. Chen
IPC分类号： H01L29/08 , H01L29/51 , H01L29/78
CPC分类号： H01L29/78 , H01L29/0847 , H01L29/51 , Y10S257/90
摘要： A transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor substrate (46). Diffused regions (56, 58) are formed within semiconductor substrate (46) in order to provide source/drain regions for transistor (42). Positive charges from radiation are trapped within sidewall spacers (52, 54) thereby attracting negative charges from semiconductor substrate (46) such that a negative charge layer is created between diffused region (56) and gate edge (50a) and also between diffused region (58) and gate edge (50b).
摘要翻译：晶体管（42）被提供有具有邻近半导体衬底（46）形成的栅极导体（44）并由栅极绝缘体（48）分离。侧壁间隔件（52,54）形成在栅极导体（44）和相邻的半导体衬底（46）的侧面。扩散区域（56,58）形成在半导体衬底（46）内，以便为晶体管（42）提供源极/漏极区域。来自辐射的正电荷被捕获在侧壁间隔物（52,54）内，从而从半导体衬底（46）吸引负电荷，使得在扩散区域（56）和栅极边缘（50a）之间以及扩散区域 58）和栅极边缘（50b）。

5. 发明授权

US4974051A MOS transistor with improved radiation hardness 失效
标题翻译：具有改善辐射硬度的MOS晶体管
公开(公告)号：US4974051A
公开(公告)日：1990-11-27
申请号：US150799
申请日：1988-02-01
申请人： Mishel Matloubian , Cheng-Eng D. Chen , Terence G. Blake
发明人： Mishel Matloubian , Cheng-Eng D. Chen , Terence G. Blake
IPC分类号： H01L21/76 , H01L21/74 , H01L23/482 , H01L27/10 , H01L29/78 , H01L29/786
CPC分类号： H01L23/4825 , H01L21/743 , H01L29/78609 , H01L29/78612 , H01L2924/0002
摘要： An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.
摘要翻译：公开了一种MOS晶体管，其具有用于在暴露于电离辐射之后通过隔离氧化物防止源极至漏极导通的保护环。在所描述的n沟道晶体管的例子中，相对于栅电极以自对准的方式在源极区域的边缘处形成p +区域，以便不在栅极下方延伸以接触漏极区域。即使在栅电极与场氧化物重叠的隔离场氧化物下面形成沟道，该p +区形成二极管，其阻止源 - 漏导通。该结构可以被硅化以提高串联电阻。还公开了以SOI配置形成的晶体管的示例。

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