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1. 发明申请

US20120007185A1 Novel method to tune narrow width effect with raised S/D structure 有权
标题翻译：用提高的S / D结构调整窄宽度效应的新方法
公开(公告)号：US20120007185A1
公开(公告)日：2012-01-12
申请号：US12803754
申请日：2010-07-06
申请人： Chunshan Yin , Guangyu Huang , Elgin Quek , Jae Gon Lee , Kian Ming Tan
发明人： Chunshan Yin , Guangyu Huang , Elgin Quek , Jae Gon Lee , Kian Ming Tan
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/088 , H01L21/26586 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/41783 , H01L29/6659 , H01L29/7848
摘要： A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.
摘要翻译：制造半导体器件的方法（和半导体器件）调节具有升高的源极/漏极（S / D）区域的场效应晶体管（FET）的栅极阈值（Vt）。以包括使用常规植入技术注入掺杂剂并以特定扭转角注入掺杂剂的两步工艺形成晕圈区域。在升高的S / D区域的有源边缘附近的卤素区域中的掺杂剂浓度更高并且比在凸起的S / D区域的内部区域内的掺杂剂浓度更深。结果，有源边缘区域附近的Vt被调节并且与有源中心区域处的Vt不同，从而为具有不同宽度的FET获得相同或相似的Vt。

2. 发明申请

US20120007180A1 FinFET with novel body contact for multiple Vt applications 有权
标题翻译： FinFET具有新的身体接触，适用于多种Vt应用
公开(公告)号：US20120007180A1
公开(公告)日：2012-01-12
申请号：US12803776
申请日：2010-07-06
申请人： Chunshan Yin , Kian Ming Tan , Jae Gon Lee
发明人： Chunshan Yin , Kian Ming Tan , Jae Gon Lee
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/785 , H01L29/66795
摘要： FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.
摘要翻译： FinFET器件形成有能够制造具有不同栅极阈值电压（Vt）的这种器件的体接触结构。形成身体接触层以接触栅电极（接触），从而能够实现正向偏置和Vt的减小。提供了两种制造方法（和结果）。在一种方法中，栅电极（硅基）和体接触层（硅）通过生长的外延连接，该外延合并形成电接触的两个结构。在另一种方法中，形成与栅电极（合适的导电材料）和体接触层相交的通孔，并且填充有导电材料以电连接两个结构。因此，可以为不同的应用制造具有不同Vt的各种FinFET。

3. 发明授权

US08785287B2 Method to tune narrow width effect with raised S/D structure 有权
标题翻译：用提高的S / D结构调整窄宽度效应的方法
公开(公告)号：US08785287B2
公开(公告)日：2014-07-22
申请号：US12803754
申请日：2010-07-06
申请人： Chunshan Yin , Guangyu Huang , Elgin Quek , Jae Gon Lee , Kian Ming Tan
发明人： Chunshan Yin , Guangyu Huang , Elgin Quek , Jae Gon Lee , Kian Ming Tan
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L27/088 , H01L21/26586 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/41783 , H01L29/6659 , H01L29/7848
摘要： A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.
摘要翻译：制造半导体器件的方法（和半导体器件）调节具有升高的源极/漏极（S / D）区域的场效应晶体管（FET）的栅极阈值（Vt）。以包括使用常规植入技术注入掺杂剂并以特定扭转角注入掺杂剂的两步工艺形成晕圈区域。在升高的S / D区域的有源边缘附近的卤素区域中的掺杂剂浓度更高并且比在凸起的S / D区域的内部区域内的掺杂剂浓度更深。结果，有源边缘区域附近的Vt被调节并且与有源中心区域处的Vt不同，从而为具有不同宽度的FET获得相同或相似的Vt。

4. 发明授权

US08735984B2 FinFET with novel body contact for multiple Vt applications 有权
标题翻译： FinFET具有新的身体接触，适用于多种Vt应用
公开(公告)号：US08735984B2
公开(公告)日：2014-05-27
申请号：US12803776
申请日：2010-07-06
申请人： Chunshan Yin , Kian Ming Tan , Jae Gon Lee
发明人： Chunshan Yin , Kian Ming Tan , Jae Gon Lee
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L29/785 , H01L29/66795
摘要： FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.
摘要翻译： FinFET器件形成有能够制造具有不同栅极阈值电压（Vt）的这种器件的体接触结构。形成身体接触层以接触栅电极（接触），从而能够实现正向偏置和Vt的减小。提供了两种制造方法（和结果）。在一种方法中，栅电极（硅基）和体接触层（硅）通过生长的外延连接，该外延合并形成电接触的两个结构。在另一种方法中，形成与栅电极（合适的导电材料）和体接触层相交的通孔，并且填充有导电材料以电连接两个结构。因此，可以为不同的应用制造具有不同Vt的各种FinFET。

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