专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06875709B2 Application of a supercritical CO2 system for curing low k dielectric materials 失效
标题翻译：应用超临界CO2系统固化低k电介质材料
公开(公告)号：US06875709B2
公开(公告)日：2005-04-05
申请号：US10383710
申请日：2003-03-07
申请人： Chun-Hsien Lin , Henry Lo , Anthony Liu , Yu-Liang Lin
发明人： Chun-Hsien Lin , Henry Lo , Anthony Liu , Yu-Liang Lin
IPC分类号： H01L21/3105 , H01L21/312 , H01L21/768 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02134 , H01L21/02118 , H01L21/02137 , H01L21/02203 , H01L21/02282 , H01L21/02343 , H01L21/31058 , H01L21/312 , H01L21/3124 , H01L21/76826 , H01L21/76829
摘要： A method and apparatus for curing and modifying a low k dielectric layer in an interconnect structure is disclosed. A spin-on low k dielectric layer which includes an organic silsesquioxane, polyarylether, bisbenzocyclobuene, or SiLK is spin coated on a substrate. The substrate is placed in a process chamber in a supercritical CO2 system and is treated at a temperature between 30° C. and 150° C. and at a pressure from 70 to 700 atmospheres. A co-solvent such as CF3—X or F—X is added that selectively replaces C—CH3 bonds with C—CF3 or C—F bonds. Alternatively, H2O2 is employed as co-solvent to replace a halogen in a C—Z bond where Z=F, Cl, or Br with an hydroxyl group. Two co-solvents may be combined with CO2 for more flexibility. The cured dielectric layer has improved properties that include better adhesion, lower k value, increased hardness, and a higher elastic modulus.
摘要翻译：公开了一种用于固化和修饰互连结构中的低k电介质层的方法和装置。将包含有机倍半硅氧烷，聚芳醚，双苯并环丁烯或SiLK的旋涂低k电介质层旋涂在基材上。将基材置于超临界CO 2体系的处理室中，并在30℃至150℃的温度和70至700大气压的压力下进行处理。加入共溶剂如CF 3 -X或F-X，其选择性地用C-CF 3或C-F键取代C-CH 3键。或者，使用H 2 O 2作为助溶剂代替C-Z键中的卤素，其中Z = F，Cl或Br与羟基。两种共溶剂可以与二氧化碳组合以获得更大的灵活性。固化的介电层具有改进的性能，其包括更好的附着力，较低的k值，更高的硬度和更高的弹性模量。

2. 发明授权

US07338909B2 Micro-etching method to replicate alignment marks for semiconductor wafer photolithography 有权
标题翻译：用于复制半导体晶片光刻的对准标记的微蚀刻方法
公开(公告)号：US07338909B2
公开(公告)日：2008-03-04
申请号：US10872238
申请日：2004-06-18
申请人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Su , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Che Wang
发明人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Su , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Che Wang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L23/544 , H01L21/31111 , H01L21/67282 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to selectively etch the material layer overlying the targeted etching portion.
摘要翻译：一种用于局部蚀刻衬底区域的方法和装置，该方法包括提供包含工艺表面的衬底; 在工艺表面上沉积材料层; 以及施加湿蚀刻剂以覆盖所述工艺表面的目标蚀刻部分，同时排除相邻的周围区域以选择性地蚀刻覆盖所述目标蚀刻部分的所述材料层。

3. 发明申请

US20050282396A1 Micro-etching method to replicate alignment marks for semiconductor wafer photolithography 有权
标题翻译：用于复制半导体晶片光刻的对准标记的微蚀刻方法
公开(公告)号：US20050282396A1
公开(公告)日：2005-12-22
申请号：US10872238
申请日：2004-06-18
申请人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Wu , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Wang
发明人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Wu , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Wang
IPC分类号： H01L21/00 , H01L21/302 , H01L21/311 , H01L21/336 , H01L21/461 , H01L23/544
CPC分类号： H01L23/544 , H01L21/31111 , H01L21/67282 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to selectively etch the material layer overlying the targeted etching portion.
摘要翻译：一种用于局部蚀刻衬底区域的方法和装置，该方法包括提供包含工艺表面的衬底; 在工艺表面上沉积材料层; 以及施加湿蚀刻剂以覆盖所述工艺表面的目标蚀刻部分，同时排除相邻的周围区域以选择性地蚀刻覆盖所述目标蚀刻部分的所述材料层。

4. 发明申请

US20080275586A1 Novel Methodology To Realize Automatic Virtual Metrology 有权
标题翻译：实现自动虚拟计量的新方法
公开(公告)号：US20080275586A1
公开(公告)日：2008-11-06
申请号：US12025933
申请日：2008-02-05
申请人： Francis Ko , Chih-Wei Lai , Kewei Zuo , Henry Lo , Jean Wang , Ping-Hsu Chen , Chun-Hsien Lin , Chen-Hua Yu
发明人： Francis Ko , Chih-Wei Lai , Kewei Zuo , Henry Lo , Jean Wang , Ping-Hsu Chen , Chun-Hsien Lin , Chen-Hua Yu
IPC分类号： G06F17/00
CPC分类号： G05B23/0221
摘要： A method to enable wafer result prediction includes collecting manufacturing data from various semiconductor manufacturing tools and metrology tools; choosing key parameters using an autokey method based on the manufacturing data; building a virtual metrology based on the key parameters; and predicting wafer results using the virtual metrology.
摘要翻译：允许晶片结果预测的方法包括从各种半导体制造工具和计量工具收集制造数据; 使用基于制造数据的自动密钥方法选择关键参数; 基于关键参数构建虚拟计量; 并使用虚拟计量来预测晶圆结果。

5. 发明申请

US20090035883A1 Auto Routing for Optimal Uniformity Control 有权
标题翻译：自动路由优化均匀性控制
公开(公告)号：US20090035883A1
公开(公告)日：2009-02-05
申请号：US11830519
申请日：2007-07-30
申请人： Jean Wang , Francis Ko , Henry Lo , Chi-Chun Hsieh , Amy Wang , Chih-Wei Lai , Chun-Hsien Lin
发明人： Jean Wang , Francis Ko , Henry Lo , Chi-Chun Hsieh , Amy Wang , Chih-Wei Lai , Chun-Hsien Lin
IPC分类号： H01L21/66
CPC分类号： H01L22/12
摘要： A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step; providing a second plurality of production tools for performing the second process step; providing a wafer; performing the first process step on the wafer using one of the first plurality of production tools; and selecting a first route including a first production tool from the second plurality of production tools. A within-wafer uniformity of the target electrical parameter on the wafer manufactured by the first route is greater than a second route including a second production tool in the second plurality of production tools.
摘要翻译：提供了一种提高晶片内均匀性的方法。该方法包括通过第一处理步骤和第二处理步骤形成电子部件，其中电气部件具有目标电参数。该方法包括：提供用于执行第一处理步骤的第一多个生产工具; 提供用于执行所述第二处理步骤的第二多个生产工具; 提供晶片; 使用所述第一多个生产工具之一在所述晶片上执行所述第一工艺步骤; 以及从所述第二多个生产工具中选择包括第一生产工具的第一路线。由第一路径制造的晶片上的目标电参数的晶片内均匀性大于在第二多个生产工具中包括第二生产工具的第二路线。

6. 发明申请

US20080275585A1 EXTRACTION OF KEY PROCESS PARAMETER 有权
标题翻译：提取关键过程参数
公开(公告)号：US20080275585A1
公开(公告)日：2008-11-06
申请号：US12026361
申请日：2008-02-05
申请人： Chun-Hsien Lin , Francis Ko , Kewei Zuo , Henry Lo , Jean Wang
发明人： Chun-Hsien Lin , Francis Ko , Kewei Zuo , Henry Lo , Jean Wang
IPC分类号： G06F17/00
CPC分类号： G05B23/0221
摘要： A system, method, and computer readable medium for extracting a key process parameter correlative to a selected device parameter are provided. In an embodiment, the key process parameter is determined using a gene map analysis. The gene map analysis includes grouping highly correlative process parameter and determining the correlation of a group to the selected device parameter. In an embodiment, the groups having greatest correlation to the selected device parameter are displayed in a correlation matrix and/or a gene map.
摘要翻译：提供了一种用于提取与所选设备参数相关的密钥过程参数的系统，方法和计算机可读介质。在一个实施例中，使用基因图分析来确定关键过程参数。基因图分析包括对高度相关的过程参数进行分组，并确定组与所选设备参数的相关性。在一个实施例中，与所选择的设备参数具有最大相关性的组被显示在相关矩阵和/或基因图中。

7. 发明授权

US08409993B2 Method and system for controlling copper chemical mechanical polish uniformity 有权
标题翻译：控制铜化学机械抛光均匀性的方法和系统
公开(公告)号：US08409993B2
公开(公告)日：2013-04-02
申请号：US11810720
申请日：2007-06-07
申请人： Francis Ko , Chun-Hsien Lin , Jean Wang , Chih-Wei Lai , Ping-Hsu Chen , Henry Lo
发明人： Francis Ko , Chun-Hsien Lin , Jean Wang , Chih-Wei Lai , Ping-Hsu Chen , Henry Lo
IPC分类号： H01L21/302
CPC分类号： H01L22/20 , H01L21/3212 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A system and method for controlling resistivity uniformity in a Copper trench structure by controlling the CMP process is provided. A preferred embodiment comprises a system and a method in which a plurality of CMP process recipes may be created comprising at least a slurry arm position. A set of metrological data for at least one layer of the semiconductor substrate may be estimated, and an optimum CMP process recipe may be selected based on the set of metrological data. The optimum CMP process recipe may be implemented on the semiconductor substrate.
摘要翻译：提供了一种通过控制CMP工艺来控制铜沟槽结构中的电阻率均匀性的系统和方法。优选实施例包括系统和方法，其中可以创建包括至少浆料臂位置的多个CMP工艺配方。可以估计用于至少一层半导体衬底的一组计量数据，并且可以基于该组计量数据来选择最佳CMP工艺配方。可以在半导体衬底上实现最佳CMP工艺配方。

8. 发明授权

US07974728B2 System for extraction of key process parameters from fault detection classification to enable wafer prediction 有权
标题翻译：从故障检测分类中提取关键过程参数的系统，以实现晶片预测
公开(公告)号：US07974728B2
公开(公告)日：2011-07-05
申请号：US12026361
申请日：2008-02-05
申请人： Chun-Hsien Lin , Francis Ko , Kewei Zuo , Henry Lo , Jean Wang
发明人： Chun-Hsien Lin , Francis Ko , Kewei Zuo , Henry Lo , Jean Wang
IPC分类号： G06F19/00 , G06F15/18 , G06F17/18 , G05B13/02
CPC分类号： G05B23/0221
摘要： A system, method, and computer readable medium for extracting a key process parameter correlative to a selected device parameter are provided. In an embodiment, the key process parameter is determined using a gene map analysis. The gene map analysis includes grouping highly correlative process parameter and determining the correlation of a group to the selected device parameter. In an embodiment, the groups having greatest correlation to the selected device parameter are displayed in a correlation matrix and/or a gene map.
摘要翻译：提供了一种用于提取与所选设备参数相关的密钥过程参数的系统，方法和计算机可读介质。在一个实施例中，使用基因图分析来确定关键过程参数。基因图分析包括对高度相关的过程参数进行分组，并确定组与所选设备参数的相关性。在一个实施例中，与所选择的设备参数具有最大相关性的组被显示在相关矩阵和/或基因图中。

9. 发明授权

US07767471B2 Auto routing for optimal uniformity control 有权
标题翻译：自动布线，实现最佳均匀度控制
公开(公告)号：US07767471B2
公开(公告)日：2010-08-03
申请号：US11830519
申请日：2007-07-30
申请人： Jean Wang , Francis Ko , Henry Lo , Chi-Chun Hsieh , Amy Wang , Chih-Wei Lai , Chun-Hsien Lin
发明人： Jean Wang , Francis Ko , Henry Lo , Chi-Chun Hsieh , Amy Wang , Chih-Wei Lai , Chun-Hsien Lin
IPC分类号： H01L21/00 , G01R31/26
CPC分类号： H01L22/12
摘要： A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step; providing a second plurality of production tools for performing the second process step; providing a wafer; performing the first process step on the wafer using one of the first plurality of production tools; and selecting a first route including a first production tool from the second plurality of production tools. A within-wafer uniformity of the target electrical parameter on the wafer manufactured by the first route is greater than a second route including a second production tool in the second plurality of production tools.
摘要翻译：提供了一种提高晶片内均匀性的方法。该方法包括通过第一处理步骤和第二处理步骤形成电子部件，其中电气部件具有目标电参数。该方法包括提供用于执行第一处理步骤的第一多个生产工具; 提供用于执行所述第二处理步骤的第二多个生产工具; 提供晶片; 使用所述第一多个生产工具之一在所述晶片上执行所述第一工艺步骤; 以及从所述第二多个生产工具中选择包括第一生产工具的第一路线。由第一路径制造的晶片上的目标电参数的晶片内均匀性大于在第二多个生产工具中包括第二生产工具的第二路线。

10. 发明申请

US20080305563A1 Method and system for controlling copper chemical mechanical polish uniformity 有权
标题翻译：控制铜化学机械抛光均匀性的方法和系统
公开(公告)号：US20080305563A1
公开(公告)日：2008-12-11
申请号：US11810720
申请日：2007-06-07
申请人： Francis Ko , Chun-Hsien Lin , Jean Wang , Chih-Wei Lai , Ping-Hsu Chen , Henry Lo
发明人： Francis Ko , Chun-Hsien Lin , Jean Wang , Chih-Wei Lai , Ping-Hsu Chen , Henry Lo
IPC分类号： H01L21/306
CPC分类号： H01L22/20 , H01L21/3212 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A system and method for controlling resistivity uniformity in a Copper trench structure by controlling the CMP process is provided. A preferred embodiment comprises a system and a method in which a plurality of CMP process recipes may be created comprising at least a slurry arm position. A set of metrological data for at least one layer of the semiconductor substrate may be estimated, and an optimum CMP process recipe may be selected based on the set of metrological data. The optimum CMP process recipe may be implemented on the semiconductor substrate.
摘要翻译：提供了一种通过控制CMP工艺来控制铜沟槽结构中的电阻率均匀性的系统和方法。优选实施例包括系统和方法，其中可以创建包括至少浆料臂位置的多个CMP工艺配方。可以估计用于至少一层半导体衬底的一组计量数据，并且可以基于该组计量数据来选择最佳CMP工艺配方。可以在半导体衬底上实现最佳CMP工艺配方。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式