专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110159674A1 Method of Manufacturing Nonvolatile Memory Devices 审中-公开
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20110159674A1
公开(公告)日：2011-06-30
申请号：US12972117
申请日：2010-12-17
申请人： Chul Young Ham , Min Sik Jang , Sang Soo Lee
发明人： Chul Young Ham , Min Sik Jang , Sang Soo Lee
IPC分类号： H01L21/223
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： A method of manufacturing nonvolatile memory devices comprises forming a plurality of floating gates spaced from each other over a semiconductor substrate, forming a dielectric layer on a surface of the floating gates, forming a capping layer on a surface of the dielectric layer, adding impurities to the capping layer, and forming a control gate over the capping layer containing the impurities.
摘要翻译：制造非易失性存储器件的方法包括在半导体衬底上形成彼此间隔开的多个浮置栅极，在浮置栅极的表面上形成电介质层，在电介质层的表面上形成覆盖层，将杂质添加到封盖层，并在包含杂质的封盖层上形成控制栅极。

2. 发明申请

US20120074485A1 Nonvolatile Memory Device and Manufacturing Method Thereof 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20120074485A1
公开(公告)日：2012-03-29
申请号：US13312569
申请日：2011-12-06
申请人： Chul Young Ham , Min Sik Jang , Sang Soo Lee
发明人： Chul Young Ham , Min Sik Jang , Sang Soo Lee
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/42324 , H01L27/11521 , H01L29/7881
摘要： A nonvolatile memory device comprises a gate insulating layer, a floating gate and a dielectric layer sequentially formed over a semiconductor substrate, a capping layer formed over the dielectric layer, and a control gate formed over the capping layer, wherein the control gate includes nitrogen or carbon as an additive.
摘要翻译：非易失性存储器件包括栅极绝缘层，浮置栅极和依次形成在半导体衬底上的电介质层，形成在电介质层上的覆盖层，以及形成在覆盖层上的控制栅极，其中控制栅极包括氮或碳作为添加剂。

3. 发明申请

US20080003788A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080003788A1
公开(公告)日：2008-01-03
申请号：US11617188
申请日：2006-12-28
申请人： Chul Young Ham , Noh Yeal Kwak
发明人： Chul Young Ham , Noh Yeal Kwak
IPC分类号： H01L21/425
CPC分类号： H01L29/6659 , H01L27/115 , H01L27/11526 , H01L27/11534
摘要： A method of manufacturing a semiconductor device includes the steps of forming a gate for a high voltage transistor on a semiconductor substrate, forming a Double Doped Drain (DDD) junction in the semiconductor substrate by means of an ion implantation process employing a DDD mask, and removing point defects, which have occurred in the DDD junction during the ion implantation process, by means of a Defect Recovery Anneal (DRA) process.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成用于高压晶体管的栅极，通过使用DDD掩模的离子注入工艺在半导体衬底中形成双掺杂漏极（DDD）结;以及通过缺陷恢复退火（DRA）过程去除在离子注入过程中在DDD结中发生的点缺陷。

4. 发明申请

US20080124894A1 METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20080124894A1
公开(公告)日：2008-05-29
申请号：US11614084
申请日：2006-12-21
申请人： Chul Young Ham , Noh Yeal Kwak
发明人： Chul Young Ham , Noh Yeal Kwak
IPC分类号： H01L21/762
CPC分类号： H01L21/31058 , H01L21/0217 , H01L21/02282 , H01L21/02337 , H01L21/3125 , H01L21/76237
摘要： A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate. The mask layer is patterned to expose an isolation region of the substrate, the isolation region defining an active region, the isolation region and the active region being defined at least partly within the doped region. Dopants of a second type are implanted at an edge of the active region as defined by the isolation region. The isolation region of the semiconductor substrate is etched to form an isolation trench having a depth that extends below a depth of the doped region. Dopants of a third type are implanted on sidewalls of the trench in order to minimize the dopants of the second type provided on the sidewalls of the isolation trench from migrating away from the sidewalls. The trenches are filled with a dielectric layer to form an isolation structure.
摘要翻译：形成半导体器件的隔离结构的方法包括将第一类型的掺杂剂注入到半导体衬底中以在衬底中形成掺杂区域。在衬底和衬底的掺杂区域上提供掩模层。图案化掩模层以暴露衬底的隔离区域，隔离区域限定有源区域，隔离区域和有源区域至少部分地限定在掺杂区域内。第二类型的掺杂剂被注入在由隔离区限定的有源区的边缘处。蚀刻半导体衬底的隔离区域以形成具有在掺杂区域的深度之下延伸的深度的隔离沟槽。将第三类型的掺杂剂注入到沟槽的侧壁上，以使设置在隔离沟槽的侧壁上的第二类型的掺杂剂最小化，从而离开侧壁迁移。沟槽填充有介电层以形成隔离结构。

5. 发明授权

US07429519B2 Method of forming isolation layer of semiconductor device 有权
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US07429519B2
公开(公告)日：2008-09-30
申请号：US11614084
申请日：2006-12-21
申请人： Chul Young Ham , Noh Yeal Kwak
发明人： Chul Young Ham , Noh Yeal Kwak
IPC分类号： H01L21/76
CPC分类号： H01L21/31058 , H01L21/0217 , H01L21/02282 , H01L21/02337 , H01L21/3125 , H01L21/76237
摘要： A method of forming an isolation structure of a semiconductor device includes implanting dopants of a first type into a semiconductor substrate to form a doped region in the substrate. A mask layer is provided over the substrate and the doped region of the substrate. The mask layer is patterned to expose an isolation region of the substrate, the isolation region defining an active region, the isolation region and the active region being defined at least partly within the doped region. Dopants of a second type are implanted at an edge of the active region as defined by the isolation region. The isolation region of the semiconductor substrate is etched to form an isolation trench having a depth that extends below a depth of the doped region. Dopants of a third type are implanted on sidewalls of the trench in order to minimize the dopants of the second type provided on the sidewalls of the isolation trench from migrating away from the sidewalls. The trenches are filled with a dielectric layer to form an isolation structure.
摘要翻译：形成半导体器件的隔离结构的方法包括将第一类型的掺杂剂注入到半导体衬底中以在衬底中形成掺杂区域。在衬底和衬底的掺杂区域上提供掩模层。图案化掩模层以暴露衬底的隔离区域，隔离区域限定有源区域，隔离区域和有源区域至少部分地限定在掺杂区域内。第二类型的掺杂剂被注入在由隔离区限定的有源区的边缘处。蚀刻半导体衬底的隔离区域以形成具有在掺杂区域的深度之下延伸的深度的隔离沟槽。将第三类型的掺杂剂注入到沟槽的侧壁上，以使设置在隔离沟槽的侧壁上的第二类型的掺杂剂最小化，从而离开侧壁迁移。沟槽填充有介电层以形成隔离结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式