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1. 发明专利

JP2005286155A Semiconductor storage device and manufacturing method thereof 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2005286155A
公开(公告)日：2005-10-13
申请号：JP2004099062
申请日：2004-03-30
申请人： Chubu Toshiba Engineering Kk , Toshiba Corp , 中部東芝エンジニアリング株式会社 , 株式会社東芝
发明人： OKAJIMA MUTSUMI , HARA TORU
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device where the occurrence of erroneous writing is prevented by suppressing an interference effect between proximal cells in a columnar direction, and to provide a manufacturing method of the semiconductor storage device. SOLUTION: The semiconductor storage device includes a memory cell array in which memory cell transistors having laminated structures (2, 3, 8, 11, 12, 13 and 14) provided with a gate insulation film 2, floating gate electrodes (3 and 8) on this gate insulation film 2, an inter-electrode insulation film 11 on the floating gate electrodes (3 and 8), and control gate electrodes (12, 13, and 14) of the inter-electrode insulation film 11 are plurally arranged in the state of a matrix. The memory cell array is provided with an element separation insulation film 7 inserted between the floating gate electrodes (3 and 8) of the memory cell transistors adjacent in a row direction, and a columnar direction cell separation insulation film inserted between the floating gate electrodes (3 and 8) of the memory cell transistors adjacent in the columnar direction and having a specific inductive capacity smaller than 3.9. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供通过抑制柱状方向上的近端电池之间的干扰效应来防止发生错误写入的半导体存储装置，并提供半导体存储装置的制造方法。解决方案：半导体存储装置包括存储单元阵列，其中具有层叠结构（2,3,8,11,12,13和14）的存储单元晶体管具有栅极绝缘膜2，浮栅电极（3 和8）在该栅极绝缘膜2上，浮栅电极（3和8）上的电极间绝缘膜11和电极间绝缘膜11的控制栅电极（12,13和14）是多个排列成矩阵状态。存储单元阵列设置有插入在与行方向相邻的存储单元晶体管的浮置栅电极（3和8）之间的元件隔离绝缘膜7和插入在浮栅电极之间的柱状方向单元隔离绝缘膜 3和8）的存储单元晶体管在柱状方向上相邻并且具有小于3.9的比容积。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2014146776A Nonvolatile storage and manufacturing method therefor 审中-公开
标题翻译：非易失存储及其制造方法
公开(公告)号：JP2014146776A
公开(公告)日：2014-08-14
申请号：JP2013046924
申请日：2013-03-08
申请人： Toshiba Corp , 株式会社東芝
发明人： OKAJIMA MUTSUMI
IPC分类号： H01L27/105 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a nonvolatile storage which suppresses occurrence of dimensional abnormality due to side etching of upper layer wiring, or occurrence of short circuit due to inclination of the upper layer wiring, when processing an underlying memory by dry etching following to processing of the upper layer wiring, in a cross point memory.SOLUTION: At the hookup part BHU of a memory cell array MCA and upper layer wiring, an upper layer wiring material layer and a memory layer configuration layer and an interlayer insulating film are processed by dry etching, to form a pattern having a line and space pattern extending in the Y direction, and a dummy line DL interconnecting the line patterns constituting the line and space pattern. Subsequently, the dummy line DL is removed.
摘要翻译：要解决的问题：提供一种制造非易失性存储器的方法，当通过干燥处理下面的存储器时，抑制由于上层布线的侧蚀造成的尺寸异常的发生或由于上层布线的倾斜引起的短路的发生在交叉点存储器中对上层布线的处理进行蚀刻。解决方案：在存储单元阵列MCA和上层布线的连接部分BHU上，上层布线材料层和存储层配置层和层间绝缘通过干法蚀刻处理薄膜，以形成具有在Y方向上延伸的线和空间图案的图案，以及互连构成线和空间图案的线图案的虚线DL。随后，去除虚线DL。

3. 发明专利

JP2010021195A Semiconductor device, and method for manufacturing semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2010021195A
公开(公告)日：2010-01-28
申请号：JP2008178031
申请日：2008-07-08
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA KOTARO , OKAJIMA MUTSUMI , TANAKA TOSHIJI
IPC分类号： H01L21/8234 , H01L21/283 , H01L21/3205 , H01L21/8247 , H01L27/088 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving planarization precision by CMP (Chemical Mechanical Polishing) while utilizing a CMP stopper film as an end-point detecting film, and to provide a method for manufacturing the semiconductor device.
SOLUTION: A silicide layer 7a is formed on a gate electrode 3a and a silicide preventing film 4b is formed on a gate electrode 3b. CMP is applied to a sacrificial film 10, the CMP stopper film 9, and an interlayer insulating film 8 so that the silicide preventing film 4b is exposed in a first region on a semiconductor substrate 1, while CMP is applied to the sacrificial film 10 so that the CMP stopper film 9 is exposed in a second region, and thereby, the first region R1 and the second region R2 are planarized.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种利用CMP阻挡膜作为端点检测膜，通过CMP（化学机械抛光）提高平坦化精度的半导体器件，并提供一种半导体器件的制造方法。解决方案：在栅电极3a上形成硅化物层7a，在栅电极3b上形成硅化物防止膜4b。将CMP施加到牺牲膜10，CMP阻挡膜9和层间绝缘膜8，使得防硅膜4b在半导体衬底1上的第一区域中露出，同时将CMP施加到牺牲膜10上 CMP停止膜9在第二区域中露出，从而使第一区域R1和第二区域R2平坦化。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2009049338A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009049338A
公开(公告)日：2009-03-05
申请号：JP2007216748
申请日：2007-08-23
申请人： Toshiba Corp , 株式会社東芝
发明人： INABA JUNGO , INOUE DAINA , OKAJIMA MUTSUMI
IPC分类号： H01L21/3213 , H01L21/28 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11529
摘要： PROBLEM TO BE SOLVED: To make a new proposal associated with a mask layer for gate processing of a semiconductor device.
SOLUTION: A method of manufacturing the semiconductor device includes the steps of: depositing first to third mask layers on a substrate; processing the third mask layer; processing the second mask layer; slimming the second mask layer in an L/S portion and outside the L/S portion; peeling the third mask layer in the L/S portion and outside the L/S portion; forming a spacer on the second mask layer in the L/S portion and outside the L/S portion; etching the second mask layer in the L/S portion while the second mask layer outside the L/S portion is covered with resist to remove the second mask layer in the L/S portion while leaving the second mask layer outside the L/S portion; and etching the first mask layer using the spacer in the L/S portion and outside the L/S portion and the second mask layer outside the L/S portion as a mask, the spacer in the L/S portion and outside the L/S portion and the second mask layer outside the L/S portion being made into a thin film.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：制造与掩模层相关联的用于半导体器件的栅极处理的新方案。解决方案：制造半导体器件的方法包括以下步骤：在衬底上沉积第一至第三掩模层; 处理第三掩模层; 处理第二掩模层; 在L / S部分和L / S部分之外使第二掩模层减薄; 在L / S部分和L / S部分外部剥离第三掩模层; 在L / S部分的第二掩模层上并在L / S部分之外形成间隔物; 蚀刻L / S部分的第二掩模层，同时用抗蚀剂覆盖L / S部分外的第二掩模层，以除去L / S部分中的第二掩模层，同时将第二掩模层留在L / S部分之外 ; 并且使用L / S部分中的间隔物和L / S部分外部的L / S部分和第二掩模层作为掩模来蚀刻第一掩模层，L / S部分中的间隔物和L / S部分和L / S部分外的第二掩模层制成薄膜。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2007134470A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007134470A
公开(公告)日：2007-05-31
申请号：JP2005325580
申请日：2005-11-10
申请人： Toshiba Corp , 株式会社東芝
发明人： OKAJIMA MUTSUMI
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10867 , H01L27/10829
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof for controlling increase in manufacturing steps and manufacturing cost by facilitating lithography to form an element isolating region even through ultra-fine processes.
SOLUTION: A color insulating film 5 is formed to an internal wall of a trench TI where a trench capacitor is formed. Ions are guided to the part of the color insulating film 5 with ion implantation of an impurity into this trench TI from one diagonal direction. A part 5' of the color insulating film 5 to which the ions are guided is removed by etching utilizing difference in the etching rates.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件及其制造方法，用于通过促进光刻以便通过超细工艺形成元件隔离区域来控制制造步骤和制造成本的增加。解决方案：在形成沟槽电容器的沟槽TI的内壁上形成彩色绝缘膜5。通过从一个对角线方向将杂质离子注入到该沟槽TI中，将离子引导到彩色绝缘膜5的一部分。通过利用蚀刻速率的差异进行蚀刻来去除引导离子的彩色绝缘膜5的部分5'。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2008140888A Manufacturing method of nonvolatile semiconductor memory 审中-公开
标题翻译：非线性半导体存储器的制造方法
公开(公告)号：JP2008140888A
公开(公告)日：2008-06-19
申请号：JP2006324177
申请日：2006-11-30
申请人： Toshiba Corp , 株式会社東芝
发明人： OKAJIMA MUTSUMI
IPC分类号： H01L21/8247 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a nonvolatile semiconductor memory which can reduce a manufacturing cost while forming necessary wiring layers.
SOLUTION: The nonvolatile semiconductor memory is manufactured by a method wherein a first contact hole 15 is formed and a second contact hole 16 is formed while employing a resist pattern 14 for forming a first contact hole 15 for forming a connecting layer 17 electrically connecting a second conductive film 9 in a region in which a selective transistor 4 is formed to a first conductive film 7 in a region in which the selective transistor 4 is formed, and the second contact hole 16 for forming a wiring layer 18 on an interlayer insulating film 13 as a mask, then, a third conductive film is buried into the first contact hole 15 and the second contact hole 16 simultaneously to form the connecting layer 17 and the wiring layer 18.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在形成必要的布线层的同时可以降低制造成本的非易失性半导体存储器的制造方法。解决方案：通过以下方法制造非易失性半导体存储器：其中形成第一接触孔15并形成第二接触孔16，同时使用抗蚀剂图案14形成用于形成电连接层17的第一接触孔15 在其中形成选择晶体管4的区域中将第二导电膜9连接到形成选择晶体管4的区域中的第一导电膜7和用于在中间层上形成布线层18的第二接触孔16 绝缘膜13作为掩模，然后，第三导电膜同时埋入第一接触孔15和第二接触孔16中，以形成连接层17和布线层18.版权所有（C）2008， JPO＆INPIT

7. 发明专利

JP2010225993A Method of manufacturing semiconductor device, and the semiconductor device 审中-公开
标题翻译：制造半导体器件的方法和半导体器件
公开(公告)号：JP2010225993A
公开(公告)日：2010-10-07
申请号：JP2009073651
申请日：2009-03-25
申请人： Toshiba Corp , 株式会社東芝
发明人： NANSEI HIROYUKI , YABUKI SO , OKAJIMA MUTSUMI
IPC分类号： H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To substantially make a memory cell flush with a peripheral circuit during processing in a semiconductor device in which the memory cell and the peripheral cirucit part have different transistor gate structures.
SOLUTION: A manufacturing method includes the steps of: forming gate insulating films 10 and 12 for the peripheral circuit on the semiconductor substrate 1; forming a polysilicon film 11 for the peripheral circuit on the gate insulating films 10 and 12; removing a part corresponding to the memory cell on the polysilicon film 11 and the gate insulating film 10; laminating a tunnel insulating film 6 for the memory cell, a charge trapping film 7, and a pad silicon oxide film 15 on the semiconductor substrate 1; forming a pad amorphous silicon film 16 on the pad silicon oxide film 15; and removing a part corresponding to the peripheral circuit on the pad amorphous silicon film 16. When the pad amorphous silicon film 16 is removed, the thickness of the polysilicon film 11 is set so as to substantially make the memory cell flush with the peripheral circuit.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：在其中存储单元和外围电路部分具有不同的晶体管栅极结构的半导体器件中，在处理期间，使存储器单元与外围电路齐平。解决方案：一种制造方法包括以下步骤：在半导体衬底1上形成用于外围电路的栅极绝缘膜10和12; 在栅绝缘膜10和12上形成用于外围电路的多晶硅膜11; 去除与多晶硅膜11和栅极绝缘膜10上的存储单元对应的部分; 在半导体衬底1上层叠用于存储单元的隧道绝缘膜6，电荷捕获膜7和焊盘氧化硅膜15; 在焊盘氧化硅膜15上形成衬垫非晶硅膜16; 并且去除与焊盘非晶硅膜16上的外围电路对应的部分。当除去焊盘非晶硅膜16时，多晶硅膜11的厚度被设定为使得存储单元基本上与外围电路齐平。版权所有（C）2011，JPO＆INPIT

8. 发明专利

JP2008205202A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008205202A
公开(公告)日：2008-09-04
申请号：JP2007039757
申请日：2007-02-20
申请人： Toshiba Corp , 株式会社東芝
发明人： INABA JUNGO , OKAJIMA MUTSUMI , AKAHORI HIROSHI
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is highly integrated and whose speed is increased, and also to provide its manufacturing method.
SOLUTION: The semiconductor device has laminated gate structures which are formed by stacking a first insulating film 12, a charge storage layer 13, a second insulating film 14, and a control gate 15 on a semiconductor substrate 11 and is provided with: an oxide film 18 which is formed between adjacently arranged first and second gate electrodes MC and MC and between the first and second gate electrodes and whose top is higher than that of the control gate 15; and a nitride film 21 which is extended on the control gate 15, on the top of the oxide film 18 and on the side walls of the oxide film 18.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供高度集成并且速度提高的半导体器件，并且还提供其制造方法。解决方案：半导体器件具有通过在半导体衬底11上层叠第一绝缘膜12，电荷存储层13，第二绝缘膜14和控制栅极15而形成的层叠栅极结构，并且设置有：形成在相邻布置的第一和第二栅电极MC和MC之间以及第一和第二栅电极之间并且其顶部高于控制栅极15的顶部的氧化物膜18; 以及在控制栅极15上，氧化膜18的顶部和氧化膜18的侧壁上延伸的氮化物膜21。（C）2008，JPO＆INPIT

9. 发明专利

JP2005123524A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005123524A
公开(公告)日：2005-05-12
申请号：JP2003359375
申请日：2003-10-20
申请人： Toshiba Corp , 株式会社東芝
发明人： OKAJIMA MUTSUMI
IPC分类号： H01L27/10 , H01L21/00 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L29/42324
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method which improve the alignment accuracy of lithography to form an opening region at an insulating film between two-layer gates, and contributes to the downsizing of a chip and the reduction of a cost.
SOLUTION: The semiconductor device includes a nonvolatile memory cell of a stack gate structure formed by laminating a polysilicon film 103 used as a floating gate and a polysilicon film 113 used as a control gate on a semiconductor substrate 101, and transistors other than the memory cell in which the control gate and the floating gate laminated and formed on the semiconductor substrate 101 as specified above are electrically connected to each other. In the transistors other than the memory cell, conductor films 131, 132, 133 are embedded in a contact hole provided so that the hole may reach the upper face of the polysilicon film 103 from the upper face of the polysilicon film 113.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种半导体器件及其制造方法，其提高光刻的对准精度以在两层栅极之间的绝缘膜处形成开口区域，并且有助于芯片的小型化和减少的成本。解决方案：半导体器件包括通过层叠用作浮置栅极的多晶硅膜103和在半导体衬底101上用作控制栅极的多晶硅膜113形成的堆叠栅极结构的非易失性存储单元，以及除了如上所述，层叠并形成在半导体衬底101上的控制栅极和浮置栅极的存储单元彼此电连接。在存储单元以外的晶体管中，导体膜131,132,133埋设在接触孔中，所述接触孔设置成使得孔可以从多晶硅膜113的上表面到达多晶硅膜103的上表面。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2004047626A Semiconductor device and manufacturing method thereof 有权
公开(公告)号：JP2004047626A
公开(公告)日：2004-02-12
申请号：JP2002201441
申请日：2002-07-10
申请人： Toshiba Corp , 株式会社東芝
发明人： OKAJIMA MUTSUMI
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8242 , H01L21/8247 , H01L23/522 , H01L23/532 , H01L27/10 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/10885 , H01L21/76802 , H01L21/76838 , H01L21/76877 , H01L21/76889 , H01L23/5226 , H01L23/53295 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method, where the distance between adjoining wirings in a contact region is longer than conventional one, for avoiding desirable short circuit among the wirings. SOLUTION: A semiconductor device 100 comprises a conductor 130 provided inside or on the surface of a semiconductor substrate 110, an insulating layer 1450 provided on the surface of the semiconductor substrate 110 or the conductor 130, a contact hole 160 reaching the conductor 130 by penetrating the insulating layer 150, a conductor 170 which is packed in the contact hole 160 and electrically connected to the conductor 130, and a wiring 200 which so extends as to pass a contact region C where the contact hole 160 is provided, in the surface region of the insulating layer 150, and of which at least one side contacts the conductor 170 in the contact region C. COPYRIGHT: (C)2004,JPO

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