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    • 7. 发明申请
    • System and method of determining the speed of digital application specific integrated circuits
    • 确定数字专用集成电路速度的系统和方法
    • US20060217919A1
    • 2006-09-28
    • US11330350
    • 2006-01-12
    • Christos Sotiriou
    • Christos Sotiriou
    • G06F19/00
    • G01R31/31703G01R31/3016G01R31/31708G01R31/31725
    • According to an embodiment of the invention, a system for identifying when a running speed of an integrated circuit is within an applied clock speed is provided. A monotonic circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the monotonic circuit. A comparator is configured to compare at least the completion detection signal and a clock signal, and configured to emit an error signal if the clock signal arrives before the completion detection signal. A synchronous circuit element is configured to receive at least a portion of the output data and configured to be clock driven by the clock signal. The error signal represents that the clock speed is faster than an operating speed of the monotonic circuit.
    • 根据本发明的实施例,提供了一种用于识别集成电路的运行速度何时处于施加的时钟速度内的系统。 单调电路被配置为接收输入数据并发送输出数据。 完成检测电路被配置为产生用于单调电路的完成检测信号。 比较器被配置为至少比较完成检测信号和时钟信号,并且如果时钟信号在完成检测信号之前到达则被配置为发出错误信号。 同步电路元件被配置为接收输出数据的至少一部分并被配置为由时钟信号驱动时钟。 误差信号表示时钟速度比单调电路的运行速度快。
    • 8. 发明申请
    • System and method of determining the speed of digital application specific integrated circuits
    • 确定数字专用集成电路速度的系统和方法
    • US20060156050A1
    • 2006-07-13
    • US11315309
    • 2005-12-23
    • Christos Sotiriou
    • Christos Sotiriou
    • G06F1/06
    • G01R31/31725G01R31/3016G01R31/31718
    • According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the asynchronous multi-rail circuit. A variable clock generator configured to be driven by at least the completion detection signal. A synchronous circuit element configured to receive at least a portion of the output data and configured to be clock driven by a clock signal from the variable clock generator. A period of the clock signal represents a running speed of the asynchronous circuit.
    • 根据本发明的一个实施例,提供了一种用于识别集成电路的运行速度的系统。 异步多轨电路被配置为接收输入数据并发送输出数据。 完成检测电路被配置为产生异步多轨电路的完成检测信号。 一种可变时钟发生器,被配置为至少由完成检测信号驱动。 一种同步电路元件,被配置为接收所述输出数据的至少一部分并被配置为由来自所述可变时钟发生器的时钟信号驱动的时钟。 时钟信号的周期表示异步电路的运行速度。