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    • 1. 发明授权
    • Digital phase alignment and integrated multichannel transceiver
employing same
    • 采用数字相位校准和集成多通道收发器
    • US5668830A
    • 1997-09-16
    • US642570
    • 1996-05-03
    • Christos John GeorgiouThor Arne LarsenKi Won Lee
    • Christos John GeorgiouThor Arne LarsenKi Won Lee
    • H03M9/00H04L7/033H04L25/34
    • H04L7/0338H03M9/00H04L7/005
    • A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.
    • 提供信号平滑和滤波功能以及滑动周期补偿的同步器和相位对准方法,并且允许多通道数字相位对准,总线偏移校正,在单个半导体芯片内集成多个收发器等。延迟线产生多个 的输入信号的延迟输入副本。 时钟相位调节器从参考时钟信号产生采样时钟信号。 采样时钟信号可以被相位调整以偏离输入信号。 经过一定的平滑和滤波功能后,选择逻辑检测采样时钟信号和输入副本之间的相位关系,并识别紧密同步的信号进行输出。 使用该识别的复制信号,打滑周期补偿和重新定时逻辑输出与参考时钟信号同步的补偿数据输出信号。 此外,提出了使用相位对准技术制造的集成多收发器。