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1. 发明授权

US09077325B2 Digital slew rate limiter 有权
标题翻译：数字转换速率限制器
公开(公告)号：US09077325B2
公开(公告)日：2015-07-07
申请号：US13932236
申请日：2013-07-01
申请人： Christopher Mayer , Hazarathaiah Malepati , Manish J. Manglani
发明人： Christopher Mayer , Hazarathaiah Malepati , Manish J. Manglani
IPC分类号： H03K5/12
CPC分类号： H03K5/12 , H03K19/00346
摘要： A circuit may include a detector, an approximator, a look-up table, a scaler, and an integrator. The detector may generate a first difference signal and a second different signal based on an input and an output. The approximator may generate, using a one's complement operation, an index based on approximated modulus values of the first difference signal and the second difference signal. The look-up table may select one of a plurality of scaling factors based upon the index. The scaler may adjust the first difference signal and the second difference signal based on the selected scaling factor. The integrator may generate the output based on the adjusted first difference signal and the adjusted second difference signal.
摘要翻译：电路可以包括检测器，近似器，查找表，缩放器和积分器。检测器可以基于输入和输出产生第一差分信号和第二不同信号。近似器可以使用补码运算来生成基于第一差分信号和第二差分信号的近似模数值的索引。查找表可以基于索引来选择多个缩放因子之一。缩放器可以基于所选择的缩放因子来调整第一差分信号和第二差分信号。积分器可以基于经调整的第一差分信号和调整的第二差分信号产生输出。

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