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1. 发明申请

US20140149718A1 INSTRUCTION AND LOGIC TO PROVIDE PUSHING BUFFER COPY AND STORE FUNCTIONALITY 有权
标题翻译：指令和逻辑提供推送缓冲区复制和存储功能
公开(公告)号：US20140149718A1
公开(公告)日：2014-05-29
申请号：US13687918
申请日：2012-11-28
申请人： Christopher J. Hughes , Changkyu Kim , Daehyun Kim , Victor W. Lee , Jong Soo Park
发明人： Christopher J. Hughes , Changkyu Kim , Daehyun Kim , Victor W. Lee , Jong Soo Park
IPC分类号： G06F9/38
CPC分类号： G06F9/30043 , G06F9/30036 , G06F9/30185 , G06F9/3834 , G06F9/3851 , G06F9/3887 , G06F9/544 , G06F12/0815 , G06F12/084 , G06F12/0875 , G06F2212/452 , G06F2212/60 , G06F2212/621 , Y02D10/13
摘要： Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.
摘要翻译：说明和逻辑提供推送缓冲区复制和存储功能。一些实施例包括第一硬件线程或处理核心，以及第二硬件线程或处理核心，高速缓存，用于存储由第二硬件线程或处理核心可访问的共享存储器地址的高速缓存行中的高速缓存相干数据。响应于对指定源数据操作数，所述共享存储器地址作为目的地操作数的指令以及所述共享存储器地址的一个或多个所有者进行解码，一个或多个执行单元将数据从源数据操作数复制到高速缓存一致数据当所述一个或多个所有者包括所述第二硬件线程或处理核心时，由所述第二硬件线程或高速缓存中的处理核心访问的所述共享存储器地址的高速缓存行。

2. 发明授权

US09513905B2 Vector instructions to enable efficient synchronization and parallel reduction operations 有权
公开(公告)号：US09513905B2
公开(公告)日：2016-12-06
申请号：US12079774
申请日：2008-03-28
申请人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
发明人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
IPC分类号： G06F15/80 , G06F9/40 , G06K9/00 , G06F9/30 , G06F9/38 , G06T5/40 , H04N1/407 , G06K9/62
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/3885 , G06K9/6212 , G06T5/40 , H04N1/4074
摘要： In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.

3. 发明授权

US08230172B2 Gather and scatter operations in multi-level memory hierarchy 有权
标题翻译：在多级内存层次结构中收集和分散操作
公开(公告)号：US08230172B2
公开(公告)日：2012-07-24
申请号：US12630826
申请日：2009-12-03
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
摘要翻译：描述与多级缓存中的收集或散布操作有关的方法和装置。在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。还描述和要求保护其他实施例。

4. 发明申请

US20090249026A1 Vector instructions to enable efficient synchronization and parallel reduction operations 有权
标题翻译：用于实现高效同步和并行还原操作的矢量指令
公开(公告)号：US20090249026A1
公开(公告)日：2009-10-01
申请号：US12079774
申请日：2008-03-28
申请人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
发明人： Mikhail Smelyanskiy , Sanjeev Kumar , Daehyun Kim , Jatin Chhugani , Changkyu Kim , Christopher J. Hughes , Victor W. Lee , Anthony D. Nguyen , Yen-Kuang Chen
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30032 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/3885 , G06K9/6212 , G06T5/40 , H04N1/4074
摘要： In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器可以包括向量单元，用于响应于单个指令对多个数据元素执行操作;以及控制单元，耦合到向量单元，以将数据元素提供给向量单元，其中控制单元将使能响应于在第一掩模下执行的第一向量指令和在第二掩码下执行的第二向量指令，对至少一些数据元素执行的原子向量操作。描述和要求保护其他实施例。

5. 发明授权

US08478941B2 Gather and scatter operations in multi-level memory hierarchy 有权
公开(公告)号：US08478941B2
公开(公告)日：2013-07-02
申请号：US13557164
申请日：2012-07-24
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.

6. 发明申请

US20120290799A1 GATHER AND SCATTER OPERATIONS IN MULTI-LEVEL MEMORY HIERARCHY 有权
标题翻译：多级记忆层级中的数学和散射运算
公开(公告)号：US20120290799A1
公开(公告)日：2012-11-15
申请号：US13557164
申请日：2012-07-24
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
摘要翻译：描述与多级缓存中的收集或散布操作有关的方法和装置。在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。还描述和要求保护其他实施例。

7. 发明申请

US20110138122A1 GATHER AND SCATTER OPERATIONS IN MULTI-LEVEL MEMORY HIERARCHY 有权
标题翻译：多级记忆层级中的数学和散射运算
公开(公告)号：US20110138122A1
公开(公告)日：2011-06-09
申请号：US12630826
申请日：2009-12-03
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
摘要翻译：描述与多级缓存中的收集或散布操作有关的方法和装置。在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。还描述和要求保护其他实施例。

8. 发明申请

US20120137074A1 METHOD AND APPARATUS FOR STREAM BUFFER MANAGEMENT INSTRUCTIONS 有权
标题翻译：流缓冲器管理指令的方法和装置
公开(公告)号：US20120137074A1
公开(公告)日：2012-05-31
申请号：US12955763
申请日：2010-11-29
申请人： Daehyun Kim , Changkyu Kim , Victor W. Lee , Jatin Chhugani , Nadathur Rajagopalan Satish
发明人： Daehyun Kim , Changkyu Kim , Victor W. Lee , Jatin Chhugani , Nadathur Rajagopalan Satish
IPC分类号： G06F12/08 , G06F12/02 , G06F12/16
CPC分类号： G06F12/0862 , G06F9/3004 , G06F2212/6022
摘要： A method and system to perform stream buffer management instructions in a processor. The stream buffer management instructions facilitate the creation and usage of a dedicated memory space or stream buffer of the processor in one embodiment of the invention. The dedicated memory space is a contiguous memory space and has a sequential or linear addressing scheme in one embodiment of the invention. The processor has logic to execute a stream buffer management instruction to copy data from a source memory address to a destination memory address that is specified with a desired level of memory hierarchy.
摘要翻译：一种在处理器中执行流缓冲器管理指令的方法和系统。在本发明的一个实施例中，流缓冲器管理指令有助于创建和使用处理器的专用存储空间或流缓冲器。专用存储器空间是连续存储器空间，并且在本发明的一个实施例中具有顺序或线性寻址方案。处理器具有执行流缓冲器管理指令的逻辑，以将来自源存储器地址的数据复制到用期望的存储器层级指定的目的地存储器地址。

9. 发明授权

US09727471B2 Method and apparatus for stream buffer management instructions 有权
公开(公告)号：US09727471B2
公开(公告)日：2017-08-08
申请号：US12955763
申请日：2010-11-29
申请人： Daehyun Kim , Changkyu Kim , Victor W. Lee , Jatin Chhugani , Nadathur Rajagopalan Satish
发明人： Daehyun Kim , Changkyu Kim , Victor W. Lee , Jatin Chhugani , Nadathur Rajagopalan Satish
IPC分类号： G06F12/00 , G06F12/0862 , G06F9/30
CPC分类号： G06F12/0862 , G06F9/3004 , G06F2212/6022
摘要： A method and system to perform stream buffer management instructions in a processor. The stream buffer management instructions facilitate the creation and usage of a dedicated memory space or stream buffer of the processor in one embodiment of the invention. The dedicated memory space is a contiguous memory space and has a sequential or linear addressing scheme in one embodiment of the invention. The processor has logic to execute a stream buffer management instruction to copy data from a source memory address to a destination memory address that is specified with a desired level of memory hierarchy.

10. 发明授权

US08743114B2 Methods and systems to determine conservative view cell occlusion 有权
标题翻译：确定保守观察细胞闭塞的方法和系统
公开(公告)号：US08743114B2
公开(公告)日：2014-06-03
申请号：US12234988
申请日：2008-09-22
申请人： Changkyu Kim , Jatin Chhugani , Christian Bienia , Daehyun Kim , Anthony Ngueyn , Sanjeev Kumar
发明人： Changkyu Kim , Jatin Chhugani , Christian Bienia , Daehyun Kim , Anthony Ngueyn , Sanjeev Kumar
IPC分类号： G06T15/00 , G06T15/40
CPC分类号： G06T15/40
摘要： Methods and systems to determine view cell occlusion, including to project objects of a 3-dimensional graphics environment to a 2-dimensional image plane with respect to the view point, to reduce sizes of corresponding object images, to generate an occluder map from the reduced-size object images, to compare at least a portion of the object images to the occluder map, and to identify an object as occluded with respect to the view cell when pixel depth values of the object image are greater than corresponding pixel depth values of the occluder map. Methods and systems to reduce an object image size include methods and systems to nullify pixel depth values within a radius of an edge pixel, and to determine the radius as a distance from the edge pixel to a second pixel so that a line between the view point and the second pixel is parallel with one or more of a line and a plane that is tangential to a sphere enclosing the view cell and a point on the object that corresponds to the edge pixel.
摘要翻译：确定观察细胞闭塞的方法和系统，包括将三维图形环境的对象相对于视点投影到二维图像平面，以减小相应对象图像的大小，从缩小的图像生成闭塞图将对象图像的尺寸调整为将至少一部分对象图像与遮挡物图进行比较，并且当对象图像的像素深度值大于对象图像的对应像素深度值时，识别相对于视图单元被遮挡的对象封堵器图。减少对象图像尺寸的方法和系统包括使边缘像素的半径内的像素深度值无效的方法和系统，并且将半径确定为距离边缘像素到第二像素的距离，使得视点并且第二像素平行于与包围视图单元的球体相切的线和平面以及与边缘像素对应的物体上的点的一个或多个。

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