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1. 发明授权

US07015504B2 Sidewall formation for high density polymer memory element array 有权
标题翻译：用于高密度聚合物存储元件阵列的侧壁形成
公开(公告)号：US07015504B2
公开(公告)日：2006-03-21
申请号：US10699903
申请日：2003-11-03
申请人： Christopher F. Lyons , Mark S. Chang , Sergey D. Lopatin , Ramkumar Subramanian , Patrick K. Cheung , Minh V. Ngo , Jane V. Oglesby
发明人： Christopher F. Lyons , Mark S. Chang , Sergey D. Lopatin , Ramkumar Subramanian , Patrick K. Cheung , Minh V. Ngo , Jane V. Oglesby
IPC分类号： H01L47/00 , H01L29/06 , H01L35/24 , H01L51/00
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L27/285 , H01L51/0595
摘要： Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.
摘要翻译：公开了用于增加与光刻特征相关联的存储单元的数量的系统和方法。这些系统包括通过采用各种沉积和蚀刻工艺在光刻特征的侧壁上形成的记忆元件。侧壁存储单元可以具有作为第一电极的晶片的位线，并且与第二形成的电极一起操作以激活在其间形成的有机物的一部分。

2. 发明授权

US06836398B1 System and method of forming a passive layer by a CMP process 有权
标题翻译：通过CMP工艺形成钝化层的系统和方法
公开(公告)号：US06836398B1
公开(公告)日：2004-12-28
申请号：US10284769
申请日：2002-10-31
申请人： Ramkumar Subramanian , Jane V. Oglesby , Minh Van Ngo , Mark S. Chang , Sergey D. Lopatin , Angela T. Hui , Christopher F. Lyons , Patrick K. Cheung , Ashok M. Khathuria
发明人： Ramkumar Subramanian , Jane V. Oglesby , Minh Van Ngo , Mark S. Chang , Sergey D. Lopatin , Angela T. Hui , Christopher F. Lyons , Patrick K. Cheung , Ashok M. Khathuria
IPC分类号： H01G435
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L21/3212 , H01L27/285 , H01L28/75
摘要： The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.
摘要翻译：本发明提供了通过平坦化工艺有助于形成半导体器件的系统和方法。本发明利用通常在化学机械平面化（CMP）工艺中发生的凹陷效应。在半导体器件上进行还原CMP工艺以形成无源层，而不是执行第一CMP，随后进行沉积和第二CMP以形成钝化层。还原CMP方法利用包含在电极的盘区域中形成钝化层的还原化学物质的浆料。因此，钝化层与用于形成电极的还原CMP工艺结合形成。

3. 发明授权

US06787458B1 Polymer memory device formed in via opening 失效
标题翻译：聚合物存储器件形成在通孔中
公开(公告)号：US06787458B1
公开(公告)日：2004-09-07
申请号：US10614397
申请日：2003-07-07
申请人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
发明人： Nicholas H. Tripsas , Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Angela T. Hui , Christopher F. Lyons , Ramkumar Subramanian , Sergey D. Lopatin , Minh Van Ngo , Ashok M. Khathuria , Mark S. Chang , Patrick K. Cheung , Jane V. Oglesby
IPC分类号： H01L2144
CPC分类号： H01L27/285 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.
摘要翻译：本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

4. 发明授权

US06803267B1 Silicon containing material for patterning polymeric memory element 有权
标题翻译：含硅材料用于图案化聚合物记忆元件
公开(公告)号：US06803267B1
公开(公告)日：2004-10-12
申请号：US10614484
申请日：2003-07-07
申请人： Ramkumar Subramanian , Christopher F. Lyons , Matthew S. Buynoski , Patrick K. Cheung , Angela T. Hui , Ashok M. Khathuria , Sergey D. Lopatin , Minh Van Ngo , Jane V. Oglesby , Terence C. Tong , James J. Xie
发明人： Ramkumar Subramanian , Christopher F. Lyons , Matthew S. Buynoski , Patrick K. Cheung , Angela T. Hui , Ashok M. Khathuria , Sergey D. Lopatin , Minh Van Ngo , Jane V. Oglesby , Terence C. Tong , James J. Xie
IPC分类号： H01L21336
CPC分类号： H01L27/28 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L51/0018
摘要： The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.
摘要翻译：本发明提供一种制造有机存储器件的方法，其中所述制造方法包括形成下电极，在所述下电极的表面上沉积无源材料，在所述被动材料上施加有机半导体材料，以及将所述有源半导体材料上电极通过有机半导体材料和被动材料到下电极。有机半导体材料的图案化是通过在有机半导体上沉积硅基抗蚀剂，照射硅基抗蚀剂的部分并图案化硅基抗蚀剂以除去硅基抗蚀剂的照射部分来实现的。此后，可以对暴露的有机半导体进行构图，并且可以剥离未照射的硅基抗蚀剂以暴露可用作单电池和多电池存储器件的存储器单元的有机半导体材料。分区组件可以与存储器件集成，以便于堆叠存储器件和编程，读取，写入和擦除存储器元件。

5. 发明授权

US06900488B1 Multi-cell organic memory element and methods of operating and fabricating 有权
标题翻译：多单元有机存储元件及其操作和制造方法
公开(公告)号：US06900488B1
公开(公告)日：2005-05-31
申请号：US10284946
申请日：2002-10-31
申请人： Sergey D. Lopatin , Mark S. Chang , Minh Van Ngo , Patrick K. Cheung
发明人： Sergey D. Lopatin , Mark S. Chang , Minh Van Ngo , Patrick K. Cheung
IPC分类号： H01L27/28 , H01L51/00 , H01L51/30 , H01L51/40 , H01L29/76
CPC分类号： H01L27/285 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L51/0021 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0041 , H01L51/0077 , H01L51/0078
摘要： The present invention provides a multi-cell organic memory device that can operate as a non-volatile memory device having a plurality of multi-cell structures constructed within the memory device. A lower electrode can be formed, wherein one or more passive layers are formed on top of the lower electrode. An Inter Layer Dielectric (ILD) is formed above the passive layers and lower electrode, whereby a via or other type relief is created within the ILD and an organic semiconductor material is then utilized to partially fill the via above the passive layer. The portions of the via that are not filled with organic material are filled with dielectric material, thus forming a multi-dimensional memory structure above the passive layer or layers and the lower electrode. One or more top electrodes are then added above the memory structure, whereby distinctive memory cells are created within the organic portions of the memory structure and activated (e.g., read/write) between the top electrodes and bottom electrode, respectively. In this manner, multiple storage cells can be formed within a singular organic structure thereby increasing memory device density and storage.
摘要翻译：本发明提供一种多小区有机存储装置，其可以作为具有构造在存储装置内的多个多小区结构的非易失性存储装置来操作。可以形成下电极，其中在下电极的顶部上形成一个或多个钝化层。在无源层和下电极之上形成层间电介质（ILD），由此在ILD内产生通孔或其它类型的浮雕，然后利用有机半导体材料部分地填充钝化层以上的通孔。通孔中没有填充有机材料的部分用电介质材料填充，从而在钝化层或下层电极之上形成多维存储结构。然后在存储器结构上方添加一个或多个顶部电极，由此在存储器结构的有机部分内分别创建独特的存储单元，并分别在顶部电极和底部电极之间激活（例如，读取/写入）。以这种方式，可以在单个有机结构内形成多个存储单元，从而增加存储器件密度和存储。

6. 发明授权

US06955939B1 Memory element formation with photosensitive polymer dielectric 有权
标题翻译：用光敏聚合物电介质形成记忆元件
公开(公告)号：US06955939B1
公开(公告)日：2005-10-18
申请号：US10700021
申请日：2003-11-03
申请人： Christopher F. Lyons , Terence C. Tong , Patrick K. Cheung
发明人： Christopher F. Lyons , Terence C. Tong , Patrick K. Cheung
IPC分类号： H01L21/00 , H01L27/28 , H01L35/24 , H01L51/00
CPC分类号： H01L27/285 , B82Y10/00 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/004 , Y10S977/943
摘要： A method of making organic memory devices containing organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The organic memory devices are made using a patternable, photosensitive dielectric that facilitates formation of the memory cells and mitigates the necessity of using photoresists.
摘要翻译：公开了一种制造有机存储器件的方法，所述有机存储器件包含由在两个电极之间具有可控导电介质的两个电极制成的有机存储器单元。有机存储器件使用可图案化的感光电介质来制造，这有助于形成存储单元并减轻使用光致抗蚀剂的必要性。

7. 发明授权

US07645632B2 Self aligned memory element and wordline 有权
标题翻译：自对准存储元件和字线
公开(公告)号：US07645632B2
公开(公告)日：2010-01-12
申请号：US11750724
申请日：2007-05-18
申请人： Patrick K. Cheung , Ashok M. Khathuria
发明人： Patrick K. Cheung , Ashok M. Khathuria
IPC分类号： H01L51/40
CPC分类号： H01L27/28
摘要： An organic polymer memory cell is provided having an organic polymer layer and an electrode layer formed over a first conductive (e.g., copper) layer (e.g., bitline). The memory cells are connected to a second conductive layer (e.g., forming a wordline), and more particularly the top of the electrode layer of the memory cells to the second conductive layer. Optionally, a conductivity facilitating layer is formed over the conductive layer. Dielectric material separates the memory cells. The memory cells are self-aligned with the bitlines formed in the first conductive layer and the wordlines formed in the second conductive layer.
摘要翻译：提供了一种有机聚合物记忆单元，其具有形成在第一导电（例如铜）层（例如位线）上的有机聚合物层和电极层。存储单元连接到第二导电层（例如，形成字线），更具体地，将存储器单元的电极层的顶部连接到第二导电层。可选地，导电促进层形成在导电层上。电介质材料分离存储单元。存储单元与形成在第一导电层中的位线和形成在第二导电层中的字线自对准。

8. 发明授权

US06989563B1 Flash memory cell with UV protective layer 有权
标题翻译：具有UV保护层的闪存单元
公开(公告)号：US06989563B1
公开(公告)日：2006-01-24
申请号：US10770260
申请日：2004-02-02
申请人： Krishnashree Achuthan , Patrick K. Cheung , Cyrus Tabery , Jean Y. Yang , Ning Cheng , Minh Van Ngo
发明人： Krishnashree Achuthan , Patrick K. Cheung , Cyrus Tabery , Jean Y. Yang , Ning Cheng , Minh Van Ngo
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , H01L23/53295 , H01L23/552 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing and planarizing an interlevel dielectric layer over the charge trapping dielectric flash memory cell and depositing over the planarized interlevel dielectric layer at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material.
摘要翻译：一种保护电荷捕获电介质闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造电荷俘获电介质闪存单元; 在电荷俘获电介质闪存单元上沉积和平坦化层间电介质层，并在平坦化的层间电介质层上沉积至少一个UV保护层，UV保护层包括基本上不透紫外线的材料。

9. 发明授权

US06274443B1 Simplified graded LDD transistor using controlled polysilicon gate profile 有权
标题翻译：使用受控多晶硅栅极配置的简化分级LDD晶体管
公开(公告)号：US06274443B1
公开(公告)日：2001-08-14
申请号：US09162116
申请日：1998-09-28
申请人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
发明人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
IPC分类号： H01L21336
CPC分类号： H01L29/66598 , H01L21/266 , H01L21/28123 , H01L21/823814 , H01L29/665 , H01L29/6659
摘要： An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having gradual doping profiles and reduced process complexity is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles. Since the LDD structures are spaced away from the edges of the second polysilicon gates, the lateral diffusion of the LDD structures into the channel due to rapid thermal annealing is reduced.
摘要翻译：通过在半导体衬底上形成栅氧化层，制造具有逐渐掺杂分布和降低工艺复杂度的LDD结构的超大规模CMOS集成电路半导体器件; 在所述栅极氧化物层上形成多晶硅层; 在所述多晶硅层上形成第一掩模层; 图案化和蚀刻第一掩模层以形成第一栅极掩模; 各向异性地蚀刻所述多晶硅层以形成第一多晶硅栅极，其中所述第一多晶硅栅极具有具有倾斜轮廓的侧壁，并且所述倾斜轮廓在所述LDD结构的离子注入期间用作掩模，以使所得到的LDD结构远离所述第二多晶硅的边缘随后将形成具有基本垂直轮廓的多晶硅栅极。由于LDD结构与第二多晶硅栅极的边缘间隔开，所以LDD结构由于快速热退火而向沟道中的横向扩散减小。

10. 发明授权

US06350639B1 Simplified graded LDD transistor using controlled polysilicon gate profile 有权
标题翻译：使用受控多晶硅栅极配置的简化分级LDD晶体管
公开(公告)号：US06350639B1
公开(公告)日：2002-02-26
申请号：US09832684
申请日：2001-04-10
申请人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
发明人： Allen S. Yu , Patrick K. Cheung , Paul J. Steffan
IPC分类号： H01L218238
CPC分类号： H01L29/66598 , H01L21/266 , H01L21/28123 , H01L21/823814 , H01L29/665 , H01L29/6659
摘要： An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a first polysilicon gate, wherein the first polysilicon gate has sidewalls with sloped profiles and the sloped profiles are used as masks during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of second polysilicon gates to be formed subsequently with substantially vertical profiles.
摘要翻译：通过在半导体衬底上形成栅极氧化层制造具有LDD结构的超大规模CMOS集成电路半导体器件; 在所述栅极氧化物层上形成多晶硅层; 在所述多晶硅层上形成第一掩模层; 图案化和蚀刻第一掩模层以形成第一栅极掩模; 各向异性地蚀刻所述多晶硅层以形成第一多晶硅栅极，其中所述第一多晶硅栅极具有具有倾斜轮廓的侧壁，并且所述倾斜轮廓在所述LDD结构的离子注入期间用作掩模，以将所得到的LDD结构远离所述第二多晶硅的边缘随后将形成具有基本垂直轮廓的多晶硅栅极。

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