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1. 发明授权

US07518982B1 System and method of communicating status and protection information between cards in a communications system 有权
标题翻译：在通信系统中的卡之间传送状态和保护信息的系统和方法
公开(公告)号：US07518982B1
公开(公告)日：2009-04-14
申请号：US10678486
申请日：2003-10-03
申请人： Christopher Brown , Mark Brian Carson , Doug Wong , Claire Greenwood
发明人： Christopher Brown , Mark Brian Carson , Doug Wong , Claire Greenwood
IPC分类号： G01R31/08 , H04J3/12
CPC分类号： H04J3/1611 , H04J3/14
摘要： Described are a system and method of communicating status and protection information between cards in a communications system. The system has a plurality of cards connected to a backplane. The plurality of cards includes a tributary card and a cross-connect card for forwarding data traffic between cards in the network element. The backplane has a link that is dedicated to carrying out-of-band signals between the tributary card and the cross-connect card. The tributary card transmits information to the cross-connect card in a first out-of-band signal over the link and the cross-connect card broadcasts the information to the plurality of cards in the network element in a second out-of-band signal.
摘要翻译：描述了在通信系统中的卡之间传送状态和保护信息的系统和方法。该系统具有连接到背板的多个卡。多个卡包括用于在网络元件中的卡之间转发数据业务的支路卡和交叉连接卡。背板具有专用于在支路卡和交叉连接卡之间执行带外信号的链路。支路卡通过链路在第一带外信号中向交叉连接卡发送信息，并且交叉连接卡以第二带外信号将信息广播到网元中的多个卡。

2. 发明授权

US08059642B2 Single stage pointer and overhead processing 有权
标题翻译：单级指针和开销处理
公开(公告)号：US08059642B2
公开(公告)日：2011-11-15
申请号：US11704731
申请日：2007-02-09
申请人： Mark Brian Carson
发明人： Mark Brian Carson
IPC分类号： H04L12/28
CPC分类号： H04J3/0632 , H04J3/047 , H04J3/0623 , H04L7/005
摘要： A method and system for providing single stage pointer and overhead processing is disclosed. In accordance with one embodiment of the invention, data including bytes of each of multiple types of overhead data is received at a logical element of a communications network. The logical element includes a labeler to label the bytes of each of the multiple types of overhead data and a pointer processor to read the labeled bytes and perform specific operations corresponding to the label, wherein the bytes of at least one type of overhead data are labeled based on feedback provided by the pointer processor to the labeler.
摘要翻译：公开了一种用于提供单级指针和开销处理的方法和系统。根据本发明的一个实施例，在通信网络的逻辑元件处接收包括多种类型的开销数据中的每一种的字节的数据。逻辑元件包括标签器，用于标记多种类型的开销数据中的每一种的字节;以及指针处理器，用于读取标记的字节并执行与标签相对应的特定操作，其中至少一种类型的开销数据的字节被标记基于指针处理器向标签器提供的反馈。

3. 发明授权

US08588354B2 Egress pointer smoother 有权
标题翻译：出口指针更平滑
公开(公告)号：US08588354B2
公开(公告)日：2013-11-19
申请号：US11704732
申请日：2007-02-09
申请人： Mark Brian Carson
发明人： Mark Brian Carson
IPC分类号： H04L7/00
CPC分类号： H04J3/0632 , H04J3/047 , H04J3/0623 , H04L7/005
摘要： A method and apparatus that allows egress pointer smoothing data by evaluating the average fill of an elastic store. For one embodiment of the invention, by measuring the average fill, the 3 bytes of SOH and 87 bytes of data are taken together in each sample, and the relative phase of ingress and egress frames does not impact the fill depth calculation. For one such embodiment, the calculation is performed by summing the elastic store fill over a full row and increment/decrement decisions based on that average figure provide smooth rate of pointers coming out even as a section overhead moves through the frame.
摘要翻译：一种通过评估弹性存储器的平均填充来允许出口指针平滑数据的方法和装置。对于本发明的一个实施例，通过测量平均填充，每个样本中共有3个字节的SOH和87个字节的数据，入口和出口帧的相对相位不影响填充深度计算。对于一个这样的实施例，通过对全行的弹性存储填充和基于该平均图形的增量/减量决定相加来执行计算，即使当部分开销移动通过帧时，提供指针的平滑速率。

4. 发明申请

US20100088478A1 System for Internally Monitoring an Integrated Circuit 审中-公开
标题翻译：内部监控集成电路系统
公开(公告)号：US20100088478A1
公开(公告)日：2010-04-08
申请号：US12574032
申请日：2009-10-06
申请人： Mark Brian Carson , David William McCracken , James Paul Crossey
发明人： Mark Brian Carson , David William McCracken , James Paul Crossey
IPC分类号： G06F12/00 , G06F3/14
CPC分类号： G09G5/003 , G09G3/006 , G09G5/363 , G09G2330/08
摘要： A system for internally monitoring an integrated circuit, wherein the contents of memory locations in the integrated circuit can be displayed on a dedicated display unit via a graphical interface device provided in the integrated circuit. The system provides a built-in means for observing the internal state of both firmware and hardware (as applicable) on the integrated circuit device. This facilitates the development of, and ongoing health monitoring of, the device in any system into which it may be incorporated. The provision of a graphical interface device provides a relatively high bandwidth for the outgoing data and so allows the internal state of the device to be monitored in real time.
摘要翻译：一种用于内部监控集成电路的系统，其中集成电路中的存储器位置的内容可以经由设置在集成电路中的图形接口装置在专用显示单元上显示。该系统提供用于观察集成电路设备上固件和硬件（如适用）的内部状态的内置手段。这有助于在可并入到其中的任何系统中开发和正在进行健康监测。提供图形接口设备为输出数据提供相对较高的带宽，因此允许实时监控设备的内部状态。

5. 发明授权

US08300748B2 Marking synchronization positions in an elastic store 失效
标题翻译：在弹性存储中标记同步位置
公开(公告)号：US08300748B2
公开(公告)日：2012-10-30
申请号：US11899726
申请日：2007-09-06
申请人： Mark Brian Carson
发明人： Mark Brian Carson
IPC分类号： H04L7/00
CPC分类号： H04J3/0632 , H04J3/047 , H04J3/0623 , H04L7/005
摘要： A method and apparatus that allows egress pointer smoothing data by evaluating the average fill of an elastic store. For one embodiment of the invention, an elastic store implements a plurality of independent FIFOs, each FIFO having a write pointer and a read pointer, the write pointer including a marking pointer field and valid flag field. An incoming byte is received to a location within a traffic memory and the write pointer is used to instruct the traffic memory to indicate that the incoming bit has been received to the location. The valid flag field is set to indicate that the value at the location is currently valid.
摘要翻译：一种通过评估弹性存储器的平均填充来允许出口指针平滑数据的方法和装置。对于本发明的一个实施例，弹性存储器实现多个独立的FIFO，每个FIFO具有写指针和读指针，所述写指针包括标记指针字段和有效标志字段。输入字节被接收到业务存储器内的位置，并且写指针用于指示业务存储器指示已经接收到该进入位到该位置。有效标志字段被设置为指示该位置处的值当前是有效的。

6. 发明授权

US07876760B2 Rate adaptation 有权
标题翻译：价格适应
公开(公告)号：US07876760B2
公开(公告)日：2011-01-25
申请号：US11901743
申请日：2007-09-17
申请人： Mark Brian Carson
发明人： Mark Brian Carson
IPC分类号： H04J3/22
CPC分类号： H04J3/0632 , H04J3/047 , H04J3/0623 , H04L7/005
摘要： A method and system for providing single stage pointer and overhead processing is disclosed. In accordance with one embodiment of the invention, data including bytes of each of multiple types of overhead data is received at a logical element of a communications network. The logical element includes a labeler to label the bytes of each of the multiple types of overhead data and a pointer processor to read the labeled bytes and perform specific operations corresponding to the label, wherein the bytes of at least one type of overhead data are labeled based on feedback provided by the pointer processor to the labeler.
摘要翻译：公开了一种用于提供单级指针和开销处理的方法和系统。根据本发明的一个实施例，在通信网络的逻辑元件处接收包括多种类型的开销数据中的每一种的字节的数据。逻辑元件包括标签器，用于标记多种类型的开销数据中的每一种的字节;以及指针处理器，用于读取标记的字节并执行与标签相对应的特定操作，其中至少一种类型的开销数据的字节被标记基于指针处理器向标签器提供的反馈。

7. 发明授权

US6107890A Digital phase comparator and frequency synthesizer 失效
标题翻译：数字相位比较器和频率合成器
公开(公告)号：US6107890A
公开(公告)日：2000-08-22
申请号：US305634
申请日：1999-05-05
申请人： Mark Brian Carson , Andrew Brown
发明人： Mark Brian Carson , Andrew Brown
IPC分类号： G01R25/00 , H03D13/00 , H03L7/085 , H03L7/091
CPC分类号： H03L7/085 , G01R25/005 , H03D13/004 , H03L7/091
摘要： The phase of a pulsed test signal is measured with reference to a reference signal of constant frequency by sampling the test signal at times determined by transitions in the reference signal and comparing the sampled test signal with the output of a phase accumulator clocked by the reference signal. A resulting measurement signal represents a difference in the number of transitions occurring in the sampled test signal and a reference state signal output by the phase accumulator. The measurement signal may be averaged and integrated to obtain an error signal which may then be filtered to provide a control signal for an oscillator. A digital frequency synthesizer is provided by frequency dividing the output of the oscillator by a constant multiple to obtain the test signal and integrating an offset signal in addition to the averaged measurement signal so that the operating frequency of the oscillator is offset from a nominal frequency by an amount determined by the offset signal. The digital frequency synthesizer is suitable for use in a synchronous equipment timing source within a telecommunications multiplexer operating at a line transmission rate of 155.52 MHz.
摘要翻译：脉冲测试信号的相位参考恒定频率的参考信号，通过在由参考信号中的转变确定的时间内对测试信号进行采样来测量，并将采样的测试信号与由参考信号计时的相位累加器的输出进行比较。所得到的测量信号表示在采样的测试信号中发生的转换次数和由相位累加器输出的参考状态信号之间的差异。可以对测量信号进行平均和积分，以获得误差信号，然后将其滤波以提供振荡器的控制信号。通过将振荡器的输出频率除以恒定倍数来提供数字频率合成器，以获得测试信号并且除了平均的测量信号之外积分偏移信号，使得振荡器的工作频率从标称频率偏移由偏移信号确定的量。数字频率合成器适用于以155.52MHz的线路传输速率工作的电信多路复用器的同步设备定时源。

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