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1. 发明申请

US20060240001A1 P-cadherin antibodies 有权
公开(公告)号：US20060240001A1
公开(公告)日：2006-10-26
申请号：US11410610
申请日：2006-04-25
申请人： Christopher Bauer , Maureen Bourner , Melanie Boyle , Gerald Casperson , David Griggs , Richard Head , William Joy , Richard Mazzarella , Ralph Minter , Mark Moffat , Barrett Thiele , Todd Vanarsdale
发明人： Christopher Bauer , Maureen Bourner , Melanie Boyle , Gerald Casperson , David Griggs , Richard Head , William Joy , Richard Mazzarella , Ralph Minter , Mark Moffat , Barrett Thiele , Todd Vanarsdale
IPC分类号： A61K39/395 , C07K16/30
CPC分类号： C07K16/28 , C07K2317/21 , C07K2317/565 , C07K2317/622 , C07K2317/76 , C07K2317/92 , Y02P20/582
摘要： The present invention relates to antibodies including human antibodies and antigen-binding portions thereof that bind to P-cadherin, and that function to inhibit P-cadherin. The invention also relates to heavy and light chain immunoglobulins derived from human P-cadherin antibodies and nucleic acid molecules encoding such immunoglobulins. The present invention also relates to methods of making human P-cadherin antibodies, compositions comprising these antibodies and methods of using the antibodies and compositions. The invention also relates to transgenic animals or plants comprising nucleic acid molecules of the present invention.

2. 发明申请

US20070174597A1 Multiple-thread processor with in-pipeline, thread selectable storage 有权
公开(公告)号：US20070174597A1
公开(公告)日：2007-07-26
申请号：US11710112
申请日：2007-02-23
申请人： William Joy , Marc Tremblay , Gary Lauterbach , Joseph Chamdani
发明人： William Joy , Marc Tremblay , Gary Lauterbach , Joseph Chamdani
IPC分类号： G06F9/44
CPC分类号： G06F9/30141 , G06F9/30127 , G06F9/3804 , G06F9/3851 , G06F9/3885 , G06F9/4843 , G06F12/0842
摘要： A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.

3. 发明授权

US5727219A Virtual input/output processor utilizing an interrupt handler 失效
标题翻译：虚拟输入/输出处理器利用中断处理程序
公开(公告)号：US5727219A
公开(公告)日：1998-03-10
申请号：US854113
申请日：1997-05-09
申请人： Thomas L. Lyon , Sun-Den Chen , William Joy , Leslie D. Kohn , Charles E. Narad , Robert Yung
发明人： Thomas L. Lyon , Sun-Den Chen , William Joy , Leslie D. Kohn , Charles E. Narad , Robert Yung
IPC分类号： G06F13/10 , G06F13/28 , G06F13/38 , G06F9/46 , G06F13/24
CPC分类号： G06F13/28 , G06F13/10 , G06F13/385
摘要： A virtual I/O processor (VIOP) is implemented using a programmed I/O (PIO) unit. The PIO unit is complemented by a VIOP interrupt, a VIOP interrupt handler, and a number of VIOP data structures. Preferably, the PIO unit is further complemented with a set of dedicated I/O global registers, a number of VIOP library read/write routines for various I/O device types, and non-blocking read and write operations. During execution, these elements cooperate with each other to perform multiple sequences of programmed I/Os as if they were being performed by a dedicated I/O processor.
摘要翻译：使用编程的I / O（PIO）单元实现虚拟I / O处理器（VIOP）。 PIO单元由VIOP中断，VIOP中断处理程序和多个VIOP数据结构补充。优选地，PIO单元进一步补充有一组专用I / O全局寄存器，用于各种I / O设备类型的多个VIOP库读/写例程以及非阻塞读写操作。在执行期间，这些元件彼此协作以执行多个编程I / O序列，就像它们由专用I / O处理器执行一样。

4. 发明授权

US5083263A BISC with interconnected register ring and selectively operating portion of the ring as a conventional computer 失效
标题翻译： BISC具有互连的寄存器环，并且作为常规计算机的环的选择性操作部分
公开(公告)号：US5083263A
公开(公告)日：1992-01-21
申请号：US225343
申请日：1988-07-28
申请人： William Joy , Robert B. Garner
发明人： William Joy , Robert B. Garner
IPC分类号： G06F9/46
CPC分类号： G06F9/462 , G06F9/30127
摘要： An integer processing unit for a reduced instruction set computer having a plurality of registers arranged in groups referred to as register windows, each window register group including a number of input registers, a similar number of output registers, and a number of local registers, the register window groups being physically arranged so the input registers of each group are the same physical register as the output registers of the next adjacent register window group thereby forming one large interconnected ring of register window groups, an arrangement for designating the register window group presently active, and an arrangement for designating register window groups which are not available for use.
摘要翻译：一种用于简化指令集计算机的整数处理单元，其具有以组称为寄存器窗口排列的多个寄存器，每个窗口寄存器组包括多个输入寄存器，相似数量的输出寄存器和多个本地寄存器，寄存器窗口组被物理布置，使得每个组的输入寄存器与下一个相邻寄存器窗口组的输出寄存器相同，从而形成寄存器窗口组的一个大的互连环，用于指定当前激活的寄存器窗口组以及用于指定不可使用的寄存器窗口组的布置。

5. 发明申请

US20070016758A1 Local and Global Register Partitioning Technique 有权
标题翻译：本地和全局注册分区技术
公开(公告)号：US20070016758A1
公开(公告)日：2007-01-18
申请号：US11533314
申请日：2006-09-19
申请人： Marc Tremblay , William Joy
发明人： Marc Tremblay , William Joy
IPC分类号： G06F15/00
CPC分类号： G06F9/3891 , G06F9/30098 , G06F9/3012 , G06F9/3838 , G06F9/3853
摘要： A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each of the register file segments being associated to one of the plurality of functional units. The register file segments are partitioned into local registers and global registers. The global registers are read and written by all functional units. The local registers are read and written only by a functional unit associated with a particular register file segment. The local registers and global registers are addressed using register addresses in an address space that is separately defined for a register file segment/functional unit pair. The global registers are addressed within a selected global register range using the same register addresses for the plurality of register file segment/functional unit pairs. The local registers in a register file segment are addressed using register addresses in a local register range outside the global register range that are assigned within a single register file segment/functional unit pair. Register addresses in the local register range are the same for the plurality of register file segment/functional unit pairs and address registers locally within a register file segment/functional unit pair.
摘要翻译：具有多个功能单元的超长指令字（VLIW）处理器包括被分成多个单独寄存器文件段的多端口寄存器文件，每个寄存器文件段与多个功能单元之一相关联。寄存器文件段被划分为本地寄存器和全局寄存器。全局寄存器由所有功能单元读写。本地寄存器仅由与特定寄存器文件段相关联的功能单元读取和写入。使用寄存器文件段/功能单元对分别定义的地址空间中的寄存器地址来寻址本地寄存器和全局寄存器。使用与多个寄存器文件段/功能单元对相同的寄存器地址，在选定的全局寄存器范围内对全局寄存器进行寻址。寄存器文件段中的本地寄存器使用在单个寄存器文件段/功能单元对内分配的全局寄存器范围之外的本地寄存器范围中的寄存器地址进行寻址。本地寄存器范围中的寄存器地址对于寄存器文件段/功能单元对中本地的多个寄存器文件段/功能单元对和地址寄存器是相同的。

6. 发明授权

US07114056B2 Local and global register partitioning in a VLIW processor 有权
标题翻译： VLIW处理器中的本地和全局寄存器分区
公开(公告)号：US07114056B2
公开(公告)日：2006-09-26
申请号：US09204585
申请日：1998-12-03
申请人： Marc Tremblay , William Joy
发明人： Marc Tremblay , William Joy
IPC分类号： G06F9/30
CPC分类号： G06F9/3891 , G06F9/30098 , G06F9/3012 , G06F9/3838 , G06F9/3853
摘要： A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each of the register file segments being associated to one of the plurality of functional units. The register file segments are partitioned into local registers and global registers. The global registers are read and written by all functional units. The local registers are read and written only by a functional unit associated with a particular register file segment. The local registers and global registers are addressed using register addresses in an address space that is separately defined for a register file segment/functional unit pair. The global registers are addressed within a selected global register range using the same register addresses for the plurality of register file segment/functional unit pairs. The local registers in a register file segment are addressed using register addresses in a local register range outside the global register range that are assigned within a single register file segment/functional unit pair. Register addresses in the local register range are the same for the plurality of register file segment/functional unit pairs and address registers locally within a register file segment/functional unit pair.
摘要翻译：具有多个功能单元的超长指令字（VLIW）处理器包括被分成多个单独寄存器文件段的多端口寄存器文件，每个寄存器文件段与多个功能单元之一相关联。寄存器文件段被划分为本地寄存器和全局寄存器。全局寄存器由所有功能单元读写。本地寄存器仅由与特定寄存器文件段相关联的功能单元读取和写入。使用寄存器文件段/功能单元对分别定义的地址空间中的寄存器地址来寻址本地寄存器和全局寄存器。使用与多个寄存器文件段/功能单元对相同的寄存器地址，在选定的全局寄存器范围内对全局寄存器进行寻址。寄存器文件段中的本地寄存器使用在单个寄存器文件段/功能单元对内分配的全局寄存器范围之外的本地寄存器范围中的寄存器地址进行寻址。本地寄存器范围中的寄存器地址对于寄存器文件段/功能单元对中本地的多个寄存器文件段/功能单元对和地址寄存器是相同的。

7. 发明授权

US06343348B1 Apparatus and method for optimizing die utilization and speed performance by register file splitting 有权
标题翻译：通过寄存器文件分割优化管芯利用率和速度性能的装置和方法
公开(公告)号：US06343348B1
公开(公告)日：2002-01-29
申请号：US09204481
申请日：1998-12-03
申请人： Marc Tremblay , William Joy
发明人： Marc Tremblay , William Joy
IPC分类号： G06F1208
CPC分类号： G11C8/16
摘要： A multi-ported register file is typically metal limited to the area consumed by the circuit proportional with the square of the number of ports. A processor having a register file structure divided into a plurality of separate and independent register files forms a layout structure with an improved layout efficiency. The read ports of the total register file structure are allocated among the separate and individual register files. Each of the separate and individual register files has write ports that correspond to the total number of write ports in the total register file structure. Writes are fully broadcast so that all of the separate and individual register files are coherent.
摘要翻译：多端口寄存器文件通常金属限于电路消耗的面积与端口数量的平方成正比。具有被分成多个独立和独立的寄存器文件的寄存器文件结构的处理器形成具有改进的布局效率的布局结构。总寄存器文件结构的读端口分配在单独和单独的寄存器文件中。每个单独的和单独的寄存器文件都具有对应于总寄存器文件结构中写入端口总数的写入端口。写入完全广播，以便所有单独和单独的注册文件是一致的。

8. 发明授权

US5845325A Virtual address write back cache with address reassignment and cache block flush 失效
标题翻译：虚拟地址回写缓存，地址重新分配和缓存块刷新
公开(公告)号：US5845325A
公开(公告)日：1998-12-01
申请号：US46476
申请日：1993-04-13
申请人： William Van Loo , John Watkins , Robert Garner , William Joy , Joseph Moran , William Shannon , Ray Cheng
发明人： William Van Loo , John Watkins , Robert Garner , William Joy , Joseph Moran , William Shannon , Ray Cheng
IPC分类号： G06F12/08 , G06F12/10 , G06F15/16
CPC分类号： G06F12/1063 , G06F12/0842 , G06F12/0891
摘要： Hardware and software improvements in workstations which utilize virtual addressing in multi-user operating systems with write back caches, including operating systems which allow each user to have multiple active processes. In virtual addressing, multi-user workstations, system performance may be improved significantly by including a virtual address write back cache as one of the system elements. Data protection and the reassignment of virtual addresses are supported within such a system as well. Multiple active processes, each with its own virtual address space, and an operating system shared by those processes in a manner which is invisible to user programs. Cache "Flush" logic is used to remove selected blocks from the virtual cache when virtual addresses are to be reassigned.
摘要翻译：在具有回写高速缓存的多用户操作系统中利用虚拟寻址的工作站中的硬件和软件改进，包括允许每个用户具有多个活动进程的操作系统。在虚拟寻址中，多用户工作站可以通过将虚拟地址回写缓存作为系统元素之一来显着提高系统性能。在这样的系统中也支持数据保护和虚拟地址的重新分配。多个活动进程，每个都具有自己的虚拟地址空间，以及这些进程以用户程序不可见的方式共享的操作系统。当虚拟地址被重新分配时，缓存“Flush”逻辑用于从虚拟缓存中删除所选的块。

9. 发明授权

US07185185B2 Multiple-thread processor with in-pipeline, thread selectable storage 有权
标题翻译：多线程处理器具有管线，线程可选存储
公开(公告)号：US07185185B2
公开(公告)日：2007-02-27
申请号：US10403406
申请日：2003-03-31
申请人： William Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
发明人： William Joy , Marc Tremblay , Gary Lauterbach , Joseph I. Chamdani
IPC分类号： G06F12/12
CPC分类号： G06F9/30141 , G06F9/30127 , G06F9/3804 , G06F9/3851 , G06F9/3885 , G06F9/4843 , G06F12/0842
摘要： A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both vertical multithreading and horizontal multithreading. Vertical multithreading permits overlapping or “hiding” of cache miss wait times. In vertical multithreading, multiple hardware threads share the same processor pipeline. A hardware thread is typically a process, a lightweight process, a native thread, or the like in an operating system that supports multithreading. Horizontal multithreading increases parallelism within the processor circuit structure, for example within a single integrated circuit die that makes up a single-chip processor. To further increase system parallelism in some processor embodiments, multiple processor cores are formed in a single die. Advances in on-chip multiprocessor horizontal threading are gained as processor core sizes are reduced through technological advancements.
摘要翻译：处理器通过支持和实现垂直多线程和水平多线程来减少由于停滞和空闲而导致的浪费周期时间，并增加执行时间的比例。垂直多线程允许重叠或“隐藏”高速缓存未命中等待时间。在垂直多线程中，多个硬件线程共享相同的处理器管道。在支持多线程的操作系统中，硬件线程通常是进程，轻量级进程，本机线程等。水平多线程增加了处理器电路结构内的并行性，例如在构成单片处理器的单个集成电路管芯内。为了在一些处理器实施例中进一步增加系统并行性，在单个管芯中形成多个处理器核。通过技术进步降低了处理器核心尺寸，从而获得片上多处理器水平线程的进步。

10. 发明授权

US07117342B2 Implicitly derived register specifiers in a processor 有权
标题翻译：在处理器中隐式导出寄存器说明符
公开(公告)号：US07117342B2
公开(公告)日：2006-10-03
申请号：US09204479
申请日：1998-12-03
申请人： Marc Tremblay , William Joy
发明人： Marc Tremblay , William Joy
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30105 , G06F9/30112 , G06F9/30145 , G06F9/30163 , G06F9/30167
摘要： A processor executes an instruction set including instructions in which a register specifier is implicitly derived, based on another register specifier. One technique for implicitly deriving a register specifier is to add or subtract one from a specifically-defined register specifier. Implicit derivation of a register specifier is selectively implemented for some opcodes. A decoder decodes instructions that use implicitly-derived register specifiers and reads the explicitly-defined register. The decoder generates pointers both to the explicitly-defined register and to the implicitly-derived register. In other embodiments, a pointer to registers within a register file includes an additional bit indicating that a register read is accompanied by a read of an implicitly-derived register.
摘要翻译：处理器基于另一个寄存器说明符执行指令集，该指令集包括其中隐含地导出寄存器说明符的指令。用于隐式导出寄存器说明符的一种技术是从特定定义的寄存器说明符添加或减去寄存器说明符。一些操作码有选择地实现了寄存器说明符的隐式推导。解码器解码使用隐式导出的寄存器说明符并读取明确定义的寄存器的指令。解码器生成指向明确定义的寄存器和隐式导出寄存器的指针。在其他实施例中，寄存器文件中的寄存器指针包括指示寄存器读取伴随着隐式导出寄存器的读取的附加位。

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