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1. 发明授权

US07562319B2 Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects 有权
标题翻译：基于用于校正邻近效应的邻近效应模型幅度，在制造布局上偏移边缘片段
公开(公告)号：US07562319B2
公开(公告)日：2009-07-14
申请号：US11530426
申请日：2006-09-08
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68 , G03F7/70441
摘要： Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.
摘要翻译：用于形成用于物理集成电路设计布局的掩模制造布局的技术包括使用邻近效应模型来校正邻近效应的制造布局。执行邻近效应模型以产生初始输出。初始输出基于制造布局中的段的第一位置。第一位置从原始制造布局中的相应原始边缘移位等于初始偏置的距离。还执行该模型以基于该段的第二位置产生第二输出。第二位置从相应的原始边缘移位等于第二偏置的距离。基于初始输出和第二输出确定段的最佳偏差。基于最佳偏差，该段在制造布局中从相应的边缘移位。

2. 发明授权

US07236916B2 Structure and method of correcting proximity effects in a tri-tone attenuated phase-shifting mask 有权
标题翻译：三色衰减相移掩模校正近距离效应的结构和方法
公开(公告)号：US07236916B2
公开(公告)日：2007-06-26
申请号：US10658933
申请日：2003-09-09
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F17/50
CPC分类号： G03F1/29 , G03F1/32 , G03F1/36
摘要： A structure and method are provided for correcting the optical proximity effects on a tri-tone attenuated phase-shifting mask. An attenuated rim, formed by an opaque region and an attenuated phase-shifting region, can be kept at a predetermined width across the mask or for certain types of structures. Typically, the attenuated rim is made as large as possible to maximize the effect of the attenuated phase-shifting region while still preventing the printing of larger portions of the attenuated phase-shifting region during the development process.
摘要翻译：提供了一种结构和方法，用于校正三音衰减相移掩模上的光学邻近效应。由不透明区域和衰减相移区域形成的衰减边缘可以跨越掩模或某些类型的结构保持在预定宽度。通常，衰减的边缘被制成尽可能大以最大化衰减的相移区域的效果，同时仍然防止在显影过程中较大部分的衰减的相移区域的打印。

3. 发明授权

US06777138B2 Mask product made by selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabricat layout 有权
标题翻译：通过基于接近效应的模型幅度来选择评估点位置而制作的掩模产品，用于校正布局布局中的邻近效应
公开(公告)号：US06777138B2
公开(公告)日：2004-08-17
申请号：US10099279
申请日：2002-03-15
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G03F900
CPC分类号： G03F1/36 , G03F1/70 , Y10S977/734
摘要： Techniques provided for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Included are techniques that correct for proximity effects associated with an edge in a layout corresponding to the design layer.
摘要翻译：提供用于制造装置的技术包括形成用于物理设计层（例如集成电路的设计）的制造布局，例如掩模布局，以及识别与设计层对应的多边形的边缘上的评估点，用于校正邻近效应。包括的技术是校正与对应于设计层的布局中的边缘相关联的邻近效应。

4. 发明授权

US06539521B1 Dissection of corners in a fabrication layout for correcting proximity effects 有权
标题翻译：在制造布局中解决拐角以纠正邻近效应
公开(公告)号：US06539521B1
公开(公告)日：2003-03-25
申请号：US09675582
申请日：2000-09-29
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F1750
CPC分类号： G03F1/36
摘要： A technique for forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, includes identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. An evaluation point is determined for the edge based on a first target length for corner segments, a second target length for non-corner segments, and characteristics of the edge. It is then determined how to correct at least a portion of the edge for proximity effects based on an analysis at the evaluation point. Another technique determines an edge type of the edge of the polygon based on the first target length for corner segments, the second target length for non-corner segments, and the characteristics of the edge. Then, the edge is divided into segments based on the edge type and the characteristics of the edge. In a technique used once a segment is determined, it is then determined whether a first end of the segment is a vertex of the polygon. If so, an evaluation point is established on the segment at a distance from the vertex that is substantially greater than half a length of the segment. A correction for the segment is then based on an analysis performed at the evaluation point.
摘要翻译：用于形成诸如用于集成电路的设计的物理设计层的制造布局（例如掩模布局）的技术包括识别与用于校正邻近效应的设计层对应的多边形的边缘上的评估点。基于角段的第一目标长度，非拐角段的第二目标长度和边缘的特性来确定边缘的评估点。然后基于评估点的分析确定如何校正边缘的至少一部分以用于邻近效应。另一种技术基于角段的第一目标长度，非拐角段的第二目标长度和边缘的特征来确定多边形的边缘的边缘类型。然后，根据边缘类型和边缘的特征将边缘划分成段。在确定了段之后所使用的技术中，然后确定段的第一端是多边形的顶点。如果是这样，则在距离该顶点一定距离处的片段上建立一个评估点，该距离基本上大于片段长度的一半。然后对该段的校正基于在评估点执行的分析。

5. 发明授权

US07926004B2 Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects 有权
标题翻译：基于用于校正邻近效应的邻近效应模型幅度，在制造布局上偏移边缘片段
公开(公告)号：US07926004B2
公开(公告)日：2011-04-12
申请号：US12482276
申请日：2009-06-10
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68 , G03F7/70441
摘要： Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.
摘要翻译：用于形成用于物理集成电路设计布局的掩模制造布局的技术包括使用邻近效应模型来校正邻近效应的制造布局。执行邻近效应模型以产生初始输出。初始输出基于制造布局中的段的第一位置。第一位置从原始制造布局中的相应原始边缘移位等于初始偏置的距离。还执行该模型以基于该段的第二位置产生第二输出。第二位置从相应的原始边缘移位等于第二偏置的距离。基于初始输出和第二输出确定段的最佳偏差。基于最佳偏差，该段在制造布局中从相应的边缘移位。

6. 发明申请

US20070006118A1 Displacing Edge Segments On A Fabrication Layout Based On Proximity Effects Model Amplitudes For Correcting Proximity Effects 有权
标题翻译：基于近似效应的制造布局偏移边缘段用于校正接近效应的模型幅度
公开(公告)号：US20070006118A1
公开(公告)日：2007-01-04
申请号：US11530426
申请日：2006-09-08
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68 , G03F7/70441
摘要： Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.
摘要翻译：用于形成用于物理集成电路设计布局的掩模制造布局的技术包括使用邻近效应模型来校正邻近效应的制造布局。执行邻近效应模型以产生初始输出。初始输出基于制造布局中的段的第一位置。第一位置从原始制造布局中的相应原始边缘移位等于初始偏置的距离。还执行该模型以基于该段的第二位置产生第二输出。第二位置从相应的原始边缘移位等于第二偏置的距离。基于初始输出和第二输出确定段的最佳偏差。基于最佳偏差，该段在制造布局中从相应的边缘移位。

7. 发明授权

US07131101B2 Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects 有权
公开(公告)号：US07131101B2
公开(公告)日：2006-10-31
申请号：US10688559
申请日：2003-10-16
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68 , G03F7/70441
摘要： Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.

8. 发明授权

US06792590B1 Dissection of edges with projection points in a fabrication layout for correcting proximity effects 有权
标题翻译：在制造布局中用投影点解剖边缘以校正邻近效应
公开(公告)号：US06792590B1
公开(公告)日：2004-09-14
申请号：US09675197
申请日：2000-09-29
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F1750
CPC分类号： G03F1/36 , G03F7/70441
摘要： Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include selecting from among all edges of all polygons in a proposed layout a subset of edges for which proximity corrections are desirable. The subset of edges includes less than all the edges. Evaluation points are established only for the subset of edges. Corrections are determined for at least portions of the subset of edges based on an analysis performed at the evaluation points. Other techniques include establishing a projection point on a first edge corresponding to the design layout based on whether a vertex of a second edge is within a halo distance. An evaluation point is determined for the first edge based on the projection point and characteristics of the first edge. It is then determined how to correct at least a portion of the edge for proximity effects based on an analysis at the evaluation point.
摘要翻译：用于制造器件的技术包括形成用于物理设计层（例如集成电路的设计）的制造布局，例如掩模布局，以及识别与设计层对应的多边形的边缘上的评估点，用于校正接近度效果。技术包括在所提出的布局中从所有多边形的所有边缘中选择需要接近校正的边缘子集。边缘子集包括少于所有边缘。仅针对边缘子集建立评估点。基于在评估点执行的分析，确定边缘子集的至少部分的校正。其他技术包括基于第二边缘的顶点是否在光晕距离内，在对应于设计布局的第一边缘上建立投影点。基于投影点和第一边缘的特性，确定第一边缘的评估点。然后基于评估点的分析确定如何校正边缘的至少一部分以用于邻近效应。

9. 发明申请

US20090249266A1 Displacing Edge Segments On A Fabrication Layout Based On Proximity Effects Model Amplitudes For Correcting Proximity Effects 有权
标题翻译：基于近似效应的制造布局偏移边缘段用于校正接近效应的模型幅度
公开(公告)号：US20090249266A1
公开(公告)日：2009-10-01
申请号：US12482276
申请日：2009-06-10
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F17/50
CPC分类号： G03F1/36 , G03F1/68 , G03F7/70441
摘要： Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.
摘要翻译：用于形成用于物理集成电路设计布局的掩模制造布局的技术包括使用邻近效应模型来校正邻近效应的制造布局。执行邻近效应模型以产生初始输出。初始输出基于制造布局中的段的第一位置。第一位置从原始制造布局中的相应原始边缘移位等于初始偏置的距离。还执行该模型以基于该段的第二位置产生第二输出。第二位置从相应的原始边缘移位等于第二偏置的距离。基于初始输出和第二输出确定段的最佳偏差。基于最佳偏差，该段在制造布局中从相应的边缘移位。

10. 发明授权

US06918104B2 Dissection of printed edges from a fabrication layout for correcting proximity effects 有权
标题翻译：从制造布局解剖印刷边缘，以纠正邻近效应
公开(公告)号：US06918104B2
公开(公告)日：2005-07-12
申请号：US10346903
申请日：2003-01-17
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G03F1/00 , G03F1/36 , G06F17/50 , G03C5/00
CPC分类号： G03F1/36 , Y10T428/24802
摘要： Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.
摘要翻译：用于制造器件的技术包括形成用于物理设计层（例如集成电路的设计）的制造布局，例如掩模布局，以及识别与设计层对应的多边形的边缘上的评估点，用于校正接近度效果。技术包括通过确定边缘的任何部分是否对应于设计层中的目标边缘来校正与第一制造布局中的边缘相关联的邻近效应。第一制造布局对应于指示印刷特征层的目标边缘的设计层。如果边缘的任何部分对应于目标边缘，则确定是否在边缘上建立评估点。然后，根据评估点确定如何纠正邻近效应的边缘。在确定边缘的任何部分不对应于目标边缘的情况下，在边缘上不选择评估点。

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