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1. 发明授权

US06319644B2 Methods of reducing proximity effects in lithographic processes 有权
公开(公告)号：US06319644B2
公开(公告)日：2001-11-20
申请号：US09780407
申请日：2001-02-12
申请人： Christophe Pierrat , James E. Burdorf , William Baggenstoss , William Stanton
发明人： Christophe Pierrat , James E. Burdorf , William Baggenstoss , William Stanton
IPC分类号： G03F900
CPC分类号： G03F1/36 , G03F7/70441
摘要： Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension.

2. 发明授权

US06284419B1 Methods of reducing proximity effects in lithographic processes 有权
公开(公告)号：US06284419B1
公开(公告)日：2001-09-04
申请号：US09769603
申请日：2001-01-24
申请人： Christophe Pierrat , James E. Burdorf , William Baggenstoss , William Stanton
发明人： Christophe Pierrat , James E. Burdorf , William Baggenstoss , William Stanton
IPC分类号： G03F900
摘要： Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension.

3. 发明授权

US06120952A Methods of reducing proximity effects in lithographic processes 有权
标题翻译：降低光刻过程中邻近效应的方法
公开(公告)号：US06120952A
公开(公告)日：2000-09-19
申请号：US164786
申请日：1998-10-01
申请人： Christophe Pierrat , James E. Burdorf , William Baggenstoss , William Stanton
发明人： Christophe Pierrat , James E. Burdorf , William Baggenstoss , William Stanton
IPC分类号： G03F1/00 , G03F1/36 , G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F1/36 , G03F7/70441
摘要： Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension.
摘要翻译：描述了将集成电路图案从掩模转印到半导体衬底上的平版印刷工艺中的邻近效应的降低方法。在一个实施例中，期望的间隔被定义在要驻留在掩模上并且要被转印到基板上的主要特征之间，以及相邻的邻近效应校正特征之间。在间隔定义之后，相对于邻近效应校正特征调整主要特征的尺寸以实现期望的转移的主要特征维度。在另一个实施例中，在具有边缘的主要特征和相邻的子分辨率特征之间限定期望的间隔。主要特征的边缘相对于子分辨率特征移动以实现所需的传送主要特征维度。

4. 发明授权

US06418008B1 Enhanced capacitor shape 有权
标题翻译：增强电容器形状
公开(公告)号：US06418008B1
公开(公告)日：2002-07-09
申请号：US09798992
申请日：2001-03-06
申请人： Mark Jost , William Stanton , Christophe Pierrat
发明人： Mark Jost , William Stanton , Christophe Pierrat
IPC分类号： H01G4005
CPC分类号： H01L27/10852 , H01L21/3143 , H01L21/3212 , H01L27/10808 , H01L27/10855 , H01L28/84 , H01L28/91
摘要： A capacitor having a pear-shaped cross section is provided. In one embodiment, the pear-shaped capacitor is a stacked container capacitor used in a dynamic random access memory circuit with a bit-line-over-capacitor construction. Each capacitor is at a minimum bit line distance from all adjacent bit line contacts, and also at a minimum capacitor distance from all adjacent capacitors along a substantial portion of its perimeter.
摘要翻译：提供具有梨形截面的电容器。在一个实施例中，梨形电容器是用于具有位线电容器结构的动态随机存取存储器电路中的堆叠容器电容器。每个电容器处于与所有相邻位线触点的最小位线距离，并且在与其周边的实质部分的所有相邻电容器的最小电容器距离处。

5. 发明授权

US06238824B1 Method for designing and making photolithographic reticle, reticle, and photolithographic process 有权
标题翻译：光刻掩模版，光罩和光刻工艺的设计和制造方法
公开(公告)号：US06238824B1
公开(公告)日：2001-05-29
申请号：US09386314
申请日：1999-08-31
申请人： John R. Futrell , Christophe Pierrat , William Stanton
发明人： John R. Futrell , Christophe Pierrat , William Stanton
IPC分类号： G03F900
CPC分类号： G03F9/7003 , G03F1/36 , G03F7/70441
摘要： There are provided methods for making a reticle for use in a photolithography process, comprising generating an first reticle layout having at least one printable reticle feature, generating a modified reticle layout having the first reticle layout and at least one correction area, generating an alignment budget-containing reticle layout having at least one different printable reticle feature and at least one alignment budget border area, and removing from the modified reticle layout any area of overlap between the at least one correction area and the at least one alignment budget border area. There are also provided reticles formed according to such methods. In addition, there are provided computer-implemented methods for designing such a reticle, as well as computer readable storage media, and computer systems for use in making such reticles. In addition, there are provided photolithographic processes using such a reticle.
摘要翻译：提供了用于制造用于光刻工艺的掩模版的方法，包括产生具有至少一个可打印掩模版特征的第一掩模布局，产生具有第一掩模版布局的修改的掩模版布局和至少一个校正区域，产生对准预算具有至少一个不同的可打印标线特征和至少一个对准预算边界区域的标线布局，以及从所述修改的标线布局移除所述至少一个校正区域和所述至少一个对准预算边界区域之间的任何重叠区域。还提供根据这种方法形成的掩模版。此外，提供了用于设计这种掩模版的计算机实现的方法以及计算机可读存储介质以及用于制作这种掩模版的计算机系统。此外，提供了使用这种掩模版的光刻工艺。

6. 发明授权

US06391709B1 Enhanced capacitor shape 有权
公开(公告)号：US06391709B1
公开(公告)日：2002-05-21
申请号：US09394401
申请日：1999-09-13
申请人： Mark Jost , William Stanton , Christophe Pierrat
发明人： Mark Jost , William Stanton , Christophe Pierrat
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/3143 , H01L21/3212 , H01L27/10808 , H01L27/10855 , H01L28/84 , H01L28/91
摘要： A capacitor having a pear-shaped cross section is provided. In one embodiment, the pear-shaped capacitor is a stacked container capacitor used in a dynamic random access memory circuit with a bit-line-over- capacitor construction. Each capacitor is at a minimum bit line distance from all adjacent bit line contacts, and also at a minimum capacitor distance from all adjacent capacitors along a substantial portion of its perimeter.

7. 发明授权

US06369432B1 Enhanced capacitor shape 失效
标题翻译：增强电容器形状
公开(公告)号：US06369432B1
公开(公告)日：2002-04-09
申请号：US09028050
申请日：1998-02-23
申请人： Mark Jost , William Stanton , Christophe Pierrat
发明人： Mark Jost , William Stanton , Christophe Pierrat
IPC分类号： H01L2976
CPC分类号： H01L27/10852 , H01L21/3143 , H01L21/3212 , H01L27/10808 , H01L27/10855 , H01L28/84 , H01L28/91
摘要： A capacitor having a pear-shaped cross section is provided. In one embodiment, the pear-shaped capacitor is a stacked container capacitor used in a dynamic random access memory circuit with a bit-line-over- capacitor construction. Each capacitor is at a minimum bit line distance from all adjacent bit line contacts, and also at a minimum capacitor distance from all adjacent capacitors along a substantial portion of its perimeter.
摘要翻译：提供具有梨形截面的电容器。在一个实施例中，梨形电容器是用于具有位线电容器结构的动态随机存取存储器电路中的堆叠容器电容器。每个电容器处于与所有相邻位线触点的最小位线距离，并且在与其周边的实质部分的所有相邻电容器的最小电容器距离处。

8. 发明申请

US20060093927A1 Pattern mask with features to minimize the effect of aberrations 审中-公开
公开(公告)号：US20060093927A1
公开(公告)日：2006-05-04
申请号：US11305197
申请日：2005-12-19
申请人： Pary Baluswamy , William Stanton , William Baggenstoss
发明人： Pary Baluswamy , William Stanton , William Baggenstoss
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/36 , G03F1/26 , G03F7/70433
摘要： A semiconductor pattern mask that might otherwise exhibit three-fold symmetry, which could give rise to distorted semiconductor features in the presence of three-leaf aberration in the optical system used to expose a semiconductor wafer through the mask, is altered to break up the three-fold symmetry without altering the semiconductor features that are formed. This accomplished by adding features to the mask that break up the symmetry. One way of achieving that result is to make the added features of “sub-resolution” size that do not produce features on the exposed wafer. Another way of achieving that result is to change existing features that do form structures in such a way (e.g., with optical elements) that changes the relative phase, amplitude or other characteristic of light transmitted through those features.

9. 发明申请

US20050014078A1 Reticles and methods of forming and using the same 失效
标题翻译：织物及其形成和使用方法
公开(公告)号：US20050014078A1
公开(公告)日：2005-01-20
申请号：US10919059
申请日：2004-08-16
申请人： William Baggenstoss , Byron Burgess , Erik Byers , William Stanton
发明人： William Baggenstoss , Byron Burgess , Erik Byers , William Stanton
IPC分类号： G03F1/00 , G03F1/36 , G03F7/20 , G03F9/00
CPC分类号： G03F7/70941 , G03F1/36 , G03F1/70 , G03F7/70433
摘要： Reticles having reticle patterns suitable for reducing edge of array effects are provided. The reticle patterns have unresolvable patterns formed in the periphery areas of the reticle patterns. The unresolvable patterns are non-transparent with respect to patterning radiation. Systems incorporating the reticles are also provided. Additionally, methods of forming and using the reticles are provided.
摘要翻译：提供了具有适于减少阵列效应边缘的掩模版图案的网状物。标线图案具有在分划板图案的周边区域中形成的不可分辨图案。关于图案化辐射，不可分辨的图案是不透明的。还提供了包含标线的系统。此外，提供了形成和使用掩模版的方法。

10. 发明申请

US20050003281A1 Pattern mask with features to minimize the effect of aberrations 失效
标题翻译：具有特征的图案掩模，以最小化像差的影响
公开(公告)号：US20050003281A1
公开(公告)日：2005-01-06
申请号：US10896985
申请日：2004-07-23
申请人： Pary Baluswamy , William Stanton , William Baggenstoss
发明人： Pary Baluswamy , William Stanton , William Baggenstoss
IPC分类号： G03F1/00 , G03F1/26 , G03F1/36 , G03F7/20 , G03C5/00 , G03F9/00
CPC分类号： G03F1/36 , G03F1/26 , G03F7/70433
摘要： A semiconductor pattern mask that might otherwise exhibit three-fold symmetry, which could give rise to distorted semiconductor features in the presence of three-leaf aberration in the optical system used to expose a semiconductor wafer through the mask, is altered to break up the three-fold symmetry without altering the semiconductor features that are formed. This accomplished by adding features to the mask that break up the symmetry. One way of achieving that result is to make the added features of “sub-resolution” size that do not produce features on the exposed wafer. Another way of achieving that result is to change existing features that do form structures in such a way (e.g., with optical elements) that changes the relative phase, amplitude or other characteristic of light transmitted through those features.
摘要翻译：另外可能会出现三重对称性的半导体图形掩模，其可能在用于通过掩模暴露半导体晶片的光学系统中存在三叶像差的情况下引起失真的半导体特征，以分解三而不改变所形成的半导体特征。这通过在面具中添加特征来分解对称性来实现。实现该结果的一种方式是使得“分辨率”尺寸的附加特征在曝光的晶片上不产生特征。实现该结果的另一种方式是改变以这样一种方式形成结构的现有特征（例如，利用光学元件），其改变透过这些特征的光的相对相位，幅度或其它特性。

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